skip to main content
10.1145/1815961.1815995acmconferencesArticle/Chapter ViewAbstractPublication PagesiscaConference Proceedingsconference-collections
research-article

RETCON: transactional repair without replay

Published:19 June 2010Publication History

ABSTRACT

Over the past decade there has been a surge of academic and industrial interest in optimistic concurrency, i.e. the speculative parallel execution of code regions that have the semantics of isolation. This work analyzes scalability bottlenecks of workloads that use optimistic concurrency. We find that one common bottleneck is updates to auxiliary program data in otherwise non-conflicting operations, e.g. reference count updates and hashtable occupancy field increments.

To eliminate the performance impact of conflicts on such auxiliary data, this work proposes RETCON, a hardware mechanism that tracks the relationship between input and output values symbolically and uses this symbolic information to transparently repair the output state of a transaction at commit. RETCON is inspired by instruction replay-based mechanisms but exploits simplifying properties of the nature of computations on auxiliary data to perform repair without replay. Our experiments show that RETCON provides significant speedups for workloads that exhibit conflicts on auxiliary data, including transforming a transactionalized version of the Python interpreter from a workload that exhibits no scaling to one that exhibits near-linear scaling on 32 cores.

References

  1. The FeS2 simulator. URL http://fes2.cs.uiuc.edu/acknowledgements.html.Google ScholarGoogle Scholar
  2. The Unladen-Swallow Benchmark Suite. URL http://code.google.com/p/unladenswallow/wiki/Benchmarks.Google ScholarGoogle Scholar
  3. A. S. Al-Zawawi, V. K. Reddy, E. Rotenberg, and H. H. Akkary. Transparent Control Independence (TCI). In Proceedings of the 34th Annual International Symposium on Computer Architecture, June 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. C. Blundell, J. Devietti, E. C. Lewis, and M. M. K. Martin. Making the Fast Case Common and the Uncommon Case Simple in Unbounded Transactional Memory. In Proceedings of the 34th Annual International Symposium on Computer Architecture, June 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. C. Blundell, M. M. K. Martin, and T. Wenisch. InvisiFence: Performance-Transparent Memory Ordering in Conventional Multiprocessors. In Proceedings of the 36th Annual International Symposium on Computer Architecture, June 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. J. Bobba, K. E. Moore, H. Volos, L. Yen, M. D. Hill, M. M. Swift, and D. A. Wood. Performance Pathologies in Hardware Transactional Memory. In Proceedings of the 34th Annual International Symposium on Computer Architecture, June 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. B. D. Carlstrom, A. MacDonald, H. Chafi, J. Chung, C. C. Minh, C. Kozyrakis, and K. Olukotun. The Atomos Transactional Programming Language. In Proceedings of the SIGPLAN 2006 Conference on Programming Language Design and Implementation, June 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. S. Chaudhry, R. Cypher, M. Ekman, M. Karlsson, A. Landin, S. Yip, H. Zeffer, and M. Tremblay. Simultaneous Speculative Threading: A Novel Pipeline Architecture Implemented in Sun's ROCK Processor. In Proceedings of the 36th Annual International Symposium on Computer Architecture, June 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. M. Cintra and J. Torellas. Eliminating Squashes Through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors. In Proceedings of the Eighth Symposium on High-Performance Computer Architecture, Feb. 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. C. Click, Feb. 2009. URL http://blogs.azulsystems.com/cliff/2009/02/and-now-some-hardwaretransactional-memory-comments.htmlGoogle ScholarGoogle Scholar
  11. R. Desikan, S. Sethumadhavan, D. Burger, and S. W. Keckler. Scalable Selective Re-execution for EDGE Architectures. In Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. L. Hammond, B. D. Carlstrom, V. Wong, B. Hertzberg, M. Chen, C. Kozyrakis, and K. Olukotun. Programming with Transactional Coherence and Consistency (TCC). In Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. L. Hammond, M. Willey, and K. Olukotun. Data Speculation Support for a Chip Multiprocessor. In Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. T. Harris and S. Stipic. Abstract Nested Transactions. In Proceedings of the Second ACM SIGPLAN Workshop on Transactional Computing, Aug. 2007.Google ScholarGoogle Scholar
  15. M. Herlihy and E. Koskinen. Transactional Boosting: A Methodology for Highly-Concurrent Transactional Objects. In Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPOPP), 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. M. Herlihy and J. E. B. Moss. Transactional Memory: Architectural Support for Lock-Free Data Structures. In Proceedings of the 20th Annual International Symposium on Computer Architecture, May 1993. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. A. D. Hilton, S. Nagarakatte, and A. Roth. iCFP: Tolerating All-Level Cache Misses in In-Order Processors. In Proceedings of the 14th Symposium on High-Performance Computer Architecture, Feb. 2008.Google ScholarGoogle Scholar
  18. A. D. Hilton and A. Roth. Ginger: Control Independence Using Tag Rewriting. In Proceedings of the 34th Annual International Symposium on Computer Architecture, June 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. J. Huh, J. Chang, D. Burger, and G. S. Sohi. Coherence Decoupling: Making Use of Incoherence. In Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. K. M. Lepak and M. H. Lipasti. Temporally Silent Stores. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. J. F. Martinez and J. Torrellas. Speculative Synchronization: Applying Thread-Level Speculation to Explicitly Parallel Applications. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. C. C. Minh, J. Chung, C. Kozyrakis, and K. Olukotun. STAMP: Stanford Transactional Applications for Multi-Processing. In Proceedings of the IEEE International Symposium on Workload Characterization, 2008.Google ScholarGoogle Scholar
  23. K. E. Moore, J. Bobba, M. J. Moravan, M. D. Hill, and D. A. Wood. LogTM: Log-based Transactional Memory. In Proceedings of the 12th Symposium on High-Performance Computer Architecture, Feb. 2006.Google ScholarGoogle ScholarCross RefCross Ref
  24. M. J. Moravan, J. Bobba, K. E. Moore, L. Yen, M. D. Hill, B. Liblit, M. M. Swift, and D. A. Wood. Supporting Nested Transactional Memory in LogTM. In Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. M. Olszewski, J. Cutler, and J. G. Steffan. JudoSTM: A Dynamic Binary Rewriting Approach to Software Transactional Memory. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. S. M. Pant and G. T. Byrd. Limited Early Value Communication to Improve Performance of Transactional Memory. In Proceedings of the 23rd International Conference on Supercomputing, June 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. S. M. Pant and G. T. Byrd. A Study of Conflicting Data in TM Programs and Methods to Increase Concurrency Using Value Prediction. In Proceedings of the Sixth ACM Conference on Computing Frontiers, May 2009.Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. V. Petric, T. Sha, and A. Roth. RENO: A Rename-Based Instruction Optimizer. In Proceedings of the 32nd Annual International Symposium on Computer Architecture, June 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. R. Rajwar and J. R. Goodman. Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution. In Proceedings of the 34th Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. H. E. Ramadan, C. J. Rossbach, and E. Witchel. Dependence-Aware Transactional Memory for Increased Concurrency. In Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture, Nov. 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. N. Riley and C. Zilles. Hardware Transactional Memory Support for Lightweight Dynamic Language Evolution. In Proceedings of the 21st SIGPLAN Conference on Object-Oriented Programming, Systems, Languages and Application (OOPSLA), Oct. 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. S. R. Sarangi, W. Liu, J. Torrellas, and Y. Zhou. ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing. In Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture, Nov. 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. A. Shriraman and S. Dwarkadas. Refereeing Conflicts in Hardware Transactional Memory Systems. In Proceedings of the 23rd International Conference on Supercomputing, June 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  34. G. Sohi, S. Breach, and T. Vijaykumar. Multiscalar Processors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, June 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. S. T. Srinivasan, R. Rajwar, H. Akkary, A. Gandhi, and M. Upton. Continual Flow Pipelines. In Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. J. G. Steffan, C. B. Colohan, A. Zhai, and T. C. Mowry. Improving Value Communication for Thread-Level Speculation. In Proceedings of the Eighth Symposium on High-Performance Computer Architecture, Feb. 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. F. Tabba, A. W. Hay, and J. R. Goodman. Transactional Value Prediction. In Proceedings of the Fourth ACM SIGPLAN Workshop on Transactional Computing, Feb. 2009.Google ScholarGoogle Scholar
  38. R. Titos, M. E. Acacio, and J. M. Garcia. Speculation-Based Conflict Resolution in Hardware Transactional Memory. In Proceedings of the International Parallel and Distributed Processing Symposium Symposium, May 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  39. S. Tomić, C. Perfumo, C. Kulkarni, A. Armejach, A. Cristal, O. Unsal, T. Harris, and M. Valero. EazyHTM: Eager-Lazy Hardware Transactional Memory. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, Nov. 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  40. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, June 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. RETCON: transactional repair without replay

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in
    • Published in

      cover image ACM Conferences
      ISCA '10: Proceedings of the 37th annual international symposium on Computer architecture
      June 2010
      520 pages
      ISBN:9781450300537
      DOI:10.1145/1815961
      • cover image ACM SIGARCH Computer Architecture News
        ACM SIGARCH Computer Architecture News  Volume 38, Issue 3
        ISCA '10
        June 2010
        508 pages
        ISSN:0163-5964
        DOI:10.1145/1816038
        Issue’s Table of Contents

      Copyright © 2010 ACM

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 19 June 2010

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • research-article

      Acceptance Rates

      Overall Acceptance Rate543of3,203submissions,17%

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader
    About Cookies On This Site

    We use cookies to ensure that we give you the best experience on our website.

    Learn more

    Got it!