Abstract
This paper argues the case for the use of analytical models in FPGA architecture exploration. We show that the problem, when simplified, is amenable to formal optimization techniques such as integer linear programming. However, the simplification process may lead to inaccurate models. To test the overall methodology, we feed the resulting architectures to VPR 5.0 and quantify their performance in comparison with traditional design methodologies. Our results show that the resulting architectures are better than those found using parameter sweep techniques. In addition, we show that these architectures can be further improved by combining the accuracy of VPR 5.0 with the efficiency of analytical techniques. This is achieved using a closed loop framework which iteratively refines the analytical model using the place and route outputs from VPR.
- Balas, E. 1998. Disjunctive programming: Properties of the convex hull of feasible points. Discr. Appl. Math. 89, 1-3, 3--44. Google Scholar
Digital Library
- Banerjee, P. Sur-Kolay, S. B. A. 2009. Fast unified floorplan topology generation and sizing on heterogeneous FPGAs. In IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 28. 651--661. Google Scholar
Digital Library
- Betz, V., Campbell, W., Fang, P., Jamieson, P., Kuon, I., Luu, J., Marquardt, A., Rose, J., and Ye, A. 2008. VPR 5.0 manual. http://www.eecg.toronto.edu/vpr/.Google Scholar
- Compton, K. and Hauck, S. 2002. Reconfigurable computing: A survey of systems and software. ACM Comput. Surv. 34, 2, 171--210. Google Scholar
Digital Library
- Emmert, J. and Bhatia, D. 1999. A methodology for fast FPGA floorplanning. In Proceedings of the ACM/SIGDA 7th International Symposium on Field Programmable Gate Arrays. ACM New York, NY, USA, 47--56. Google Scholar
Digital Library
- Feng, Y. and Mehta, D. 2006. Heterogeneous floorplanning for FPGAs. In Proceedings of the IEEE International Conference on VLSI Design. 257--262. Google Scholar
Digital Library
- He, J. and Rose, J. 1993. Advantages of heterogeneous logic block architecture for FPGAs. In Proceedings of the Custom Integrated Circuits Conference. 7--4.Google Scholar
- Hutton, M. 2006. FPGA architecture design methodology. In Proceedings of the International Conference on Field Programmable Logic and Applications. 1.Google Scholar
Cross Ref
- Kahoul, A., Constantinides, G. A., Smith, A. M., and Cheung, P. Y. K. 2009. Heterogeneous architecture exploration: Analysis vs. parameter sweep. In Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC’09). 133--144. Google Scholar
Digital Library
- Kuon, I. and Rose, J. 2006. Measuring the gap between FPGAs and ASICs. In Proceedings of the 14th International Symposium on Field Programmable Gate Arrays. ACM New York, 21--30. Google Scholar
Digital Library
- Murata, H., Fujiyoshi, K., Nakatake, S., and Kajitani, Y. 1996. VLSI module placement based on rectangle-packing by thesequence-pair. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 15, 12, 1518--1524. Google Scholar
Digital Library
- Sherali, H., Smith, J., and Adams, W. 2000. Reduced first-level representations via the reformulation-linearization technique: Results, counterexamples, and computations. Discr. Appl. Math. 101, 1-3, 247--267. Google Scholar
Digital Library
- Sherali, H., Fraticelli, B., and Meller, R. 2003. Enhanced model formulations for optimal facility layout. Oper. Resear. 51, 4, 629. Google Scholar
Digital Library
- Singhal, L. and Bozorgzadeh, E. 2007. Novel multi-layer floorplanning for heterogeneous FPGAs. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’07). 613--616.Google Scholar
- Smith, A., Constantinides, G., and Cheung, P. 2005. An analytical approach to generation and exploration of reconfigurable architectures. In Proceedings of the International Conference on Field Programmable Logic and Applications. 341--346.Google Scholar
- Smith, A., Constantinides, G., and Cheung, P. 2008. Integrated floorplanning, module-selection, and architecture generation for reconfigurable devices. In IEEE Trans. VLSI Syst. 16, 6, 733--744. Google Scholar
Digital Library
- Tsay, R., Kuh, E., Center, I., and Heights, Y. 1991. A unified approach to partitioning and placement {VLSI layout}. IEEE Trans. Circ. Syst. 38, 5, 521--533.Google Scholar
Cross Ref
- Vecchietti, A., Lee, S., and Grossmann, I. 2003. Modeling of discrete/continuous optimization problems: Characterization and formulation of disjunctions and their relaxations. Comput. Chem. Engin. 27, 3, 433--448.Google Scholar
Cross Ref
Index Terms
Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods
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