Abstract
Most hardware/software (HW/SW) codesigns of Elliptic Curve Cryptography have focused on the computational aspect of the ECC hardware, and not on the system integration into a System-on-Chip (SoC) architecture. We study the impact of the communication link between CPU and coprocessor hardware for a typical ECC design, and demonstrate that the SoC may become performance-limited due to coprocessor data- and instruction-transfers. A dual strategy is proposed to remove the bottleneck: introduction of control hierarchy as well as local storage. The performance of the ECC coprocessor can be almost independent of the selection of bus protocols. Besides performance, the proposed ECC coprocessor is also optimized for scalability. Using design space exploration of a large number of system configurations of different architectures, our proposed ECC coprocessor architecture enables trade-offs between area, speed, and security.
- Aigner, H., Bock, H., Htter, M., and Wolkerstorfer, J. 2004. A low-cost ecc coprocessor for smartcards. In Proceedings of the Conference on Cryptographic Hardware and Embedded Systems. Springer, Berlin, 107--118.Google Scholar
- Batina, L., Hwang, D., Hodjat, A., Preneel, B., and Verbauwhede, I. 2005. Hardware/software co-design for hyperelliptic curve cryptography (hecc) on the 8051 p. In Proceedings of the Conference on Cryptographic Hardware and Embedded Systems. Springer, Berlin, 106--118. Google Scholar
Digital Library
- Cheung, R. C. C., Luk, W., and Cheung, P. Y. K. 2005. Reconfigurable elliptic curve cryptosystems on a chip. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’05). IEEE Computer Society, Los Alamitos, CA, 24--29. Google Scholar
Digital Library
- Coron, J.-S. 1999. Resistance against differential power analysis for elliptic curve cryptosystems. In Proceedings of the 1st International Workshop on Cryptographic Hardware and Embedded Systems (CHES’99). Springer-Verlag, 292--302. Google Scholar
Digital Library
- Groβschädl, J. 2001. A low-power bit-serial multiplier for finite fields gf(2m). In Proceedings of the 34th IEEE International Symposium on Circuits and Systems. IEEE, 37--40.Google Scholar
- Guo, X. and Schaumont, P. 2009. Optimizing the control hierarchy of an ecc coprocessor design on an fpga based soc platform. In Proceedings of 5th International Workshop on Applied Reconfigurable Computing. Springer-Verlag, Berlin, 169--180. Google Scholar
Digital Library
- Guo, X., Fan, J., Schaumont, P., and Verbauwhede, I. 2009. Programmable and parallel ecc coprocessor architecture: Tradeoffs between area, speed and security. In Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES’09). Springer, 289--303. Google Scholar
Digital Library
- Gura, N., Shantz, S. C., Eberle, H., Gupta, S., Gupta, V., Finchelstein, D., Goupy, E., and Stebila, D. 2003. An end-to-end systems approach to elliptic curve cryptography. In Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems (CHES’02). Springer-Verlag, 349--365. Google Scholar
Digital Library
- Gura, N., Patel, A., Wander, A., Eberle, H., and Shantz, S. C. 2004. Comparing elliptic curve cryptography and rsa on 8-bit cpus. In Proceedings of the Conference on Cryptographic Hardware and Embedded Systems. Springer, Berlin, 925--943.Google Scholar
- Hankerson, D., Menezes, A., and Vanstone, S. 2004. Guide to Elliptic Curve Cryptography. Springer-Verlag, Berlin. Google Scholar
Digital Library
- Hempel, G. and Hochberger, C. 2007. A resource optimized processor core for fpga based socs. In Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD’07). IEEE Computer Society, Los Alamitos, CA, 51--58. Google Scholar
Digital Library
- Hodjat, A., Hwang, D., Batina, L., and Verbauwhede, I. 2005. A hyperelliptic curve crypto coprocessor for an 8051 microcontroller. In Proceedings of the 19th IEEE Workshop on Signal Processing Systems. IEEE, 93--98.Google Scholar
- Itoh, T. and Tsujii, S. 1988. A fast algorithm for computing multiplicative inverses in gf(2m) using normal bases. In Information and Computation. Academic Press, Inc., 171--177. Google Scholar
Digital Library
- Järvinen, K. and Skyttä, J. 2008. On parallelization of high-speed processors for elliptic curve cryptography. IEEE Trans. VLSI Syst. 1162--1175. Google Scholar
Digital Library
- Koblitz, A. H., Koblitz, N., and Menezes, A. 2008. Elliptic curve cryptography: The serpentine course of a paradigm shift. http://eprint.iacr.org/2008/390.Google Scholar
- Koblitz, N. 1987. Elliptic curve cryptosystems. Mathematics of computation. Math. Comput. 48, 177, 203--209.Google Scholar
- Koblitz, N. 1990. A family of jacobians suitable for discrete log cryptosystems. In Proceedings of the 8th Annual International Cryptology Conference on Advances in Cryptology (CRYPTO’88). Springer-Verlag, 94--99. Google Scholar
Digital Library
- Koschuch, M., Lechner, J., Weitzer, A., Groβschädl, J., Szekely, A., Tillich, S., and Wolkerstorfer, J. 2006. Hardware/software co-design of elliptic curve cryptography on an 8051 microcontroller. In Proceedings of the Conference on Cryptographic Hardware and Embedded Systems. Springer, Berlin, 430--444. Google Scholar
Digital Library
- Kumar, S. and Paar, C. 2004. Reconfigurable instruction set extension for enabling ecc on an 8-bit processor. In Proceedings of the Conference on Field Programmable Logic and Application. Springer, Berlin, 586--585.Google Scholar
- Kumar, S., Wollinger, T., and Paar, C. 2006. Optimum digit serial gf(2m) multipliers for curve-based cryptography. IEEE Trans. Comput. 55, 10, 1306--1311. Google Scholar
Digital Library
- López, J. and Dahab, R. 1999. Fast multiplication on elliptic curves over gf(2m) without precomputation. In Proceedings of the 1st International Workshop on Cryptographic Hardware and Embedded Systems (CHES’99). Springer-Verlag, 316--327. Google Scholar
Digital Library
- Miller, V. S. 1986. Use of elliptic curves in cryptography. In CRYPTO’85: Advances in Cryptology. Springer-Verlag, 417--426. Google Scholar
Digital Library
- NIST. 2000. Digital signature standard. FIPS PUB 186-2 Federal Information Processing Standard. NIST.Google Scholar
- Orlando, G. and Paar, C. 2000. A high performance reconfigurable elliptic curve processor for gf(2m). In Proceedings of the 2nd International Workshop on Cryptographic Hardware and Embedded Systems (CHES’00). Springer-Verlag, 41--56. Google Scholar
Digital Library
- Rodríguez-Henríquez, F., Saqib, N. A., Díaz-Pèrez, A., and Koc, C. K. 2006. Cryptographic Algorithms on Reconfigurable Hardware (Signals and Communication Technology). Springer-Verlag. Google Scholar
Digital Library
- Sakiyama, K., Batina, L., Preneel, B., and Verbauwhede, I. 2006. Superscalar coprocessor for high-speed curve-based cryptography. In Proceedings of the Conference on Cryptographic Hardware and Embedded Systems. Springer, Berlin, 415--429. Google Scholar
Digital Library
- Schaumont, P., Ching, D., and Verbauwhede, I. 2006. An interactive codesign environment for domain-specific coprocessors. ACM Trans. Des. Autom. Electron. Syst. 11, 1, 70--87. Google Scholar
Digital Library
Index Terms
Optimized System-on-Chip Integration of a Programmable ECC Coprocessor
Recommendations
System-on-a-programmable-chip development platforms in the classroom
This paper describes the authors' experiences using a system-on-a-programmable-chip (SOPC) approach to support the development of design projects for upper-level undergraduate students in their electrical and computer engineering curriculum. Commercial ...
Elliptic Curve Cryptography on FPGA for Low-Power Applications
Elliptic curve cryptography has generated a lot of research interest due to its ability to provide greater security per bit compared to public key systems such as RSA. The designer of an elliptic curve hardware accelerator is faced with many choices at ...
Implementation of FFT on General-Purpose Architectures for FPGA
This paper describes two general-purpose architectures targeted to Field Programmable Gate Array FPGA implementation. The first architecture is based on the coupling of a coarse-grain reconfigurable array with a general-purpose processor core. The ...






Comments