Abstract
With the gradually fading distinction between hardware and software, it is now possible to relocate tasks from a microprocessor to reconfigurable logic and vice versa. However, existing hardware-software scheduling can rarely cope with such runtime task relocation. In this work, we propose a new Relocatable Hardware-Software Scheduling (RHSS) method that not only can be applied to dynamically relocatable hardware-software tasks, but also increases the reconfigurable hardware resource utilization, reduces the reconfigurable hardware resource fragmentation with realistic placement methods, and makes best efforts at meeting the real-time constraints of tasks. The feasibility of the proposed relocatable hardware-software scheduling algorithm was proved by applying it to some randomly generated examples and a real dynamically reconfigurable network security system example. Compared to the quadratic time complexity of the state-of-the-art Adaptive Hardware-Software Allocation (AHSA) method, RHSS is linear in time complexity, and improves the reconfigurable hardware utilization by as much as 117.8%. The scheduling and placement time and the memory usage are also drastically reduced by as much as 89.5% and 96.4%, respectively.
- Abeni, L. and Buttazzo, G. 1998. Integrating multimedia applications in hard real-time systems. In Proceedings of the 19th IEEE Real-Time Systems Symposium. IEEE Computer Society, 4--13. Google Scholar
Digital Library
- Ahmadinia, A. and Teich, J. 2003. Speeding up online placement for Xilinx FPGAs by reducing configuration overhead. In Proceedings of the IFIP International Conference on VLSI-SoC. 118--122.Google Scholar
- Ahmadinia, A., Bobda, C., Bednara, M., and Teich, J. 2004. A new approach for on-line placement on reconfigurable devices. In Proceedings of the International Parallel and Distributed Processing Symposium. IEEE CS Press, 134.Google Scholar
- Ahmadinia, A., Bobda, C., Fekete, S. P., Teich, J., and van der Veen, J. C. 2004. Optimal routing-conscious dynamic placement for reconfigurable devices. In Proceedings of the 14th International Conference on Field-Programmable Logic and Applications. Lecture Notes in Computer Science, vol. 3203. Springer, 847--851.Google Scholar
- Ahmadinia, A., Bobda, C., and Teich, J. 2005. Online placement for dynamically reconfigurable devices. Int. J. Embed. Syst. 1, 3--4, 165--178.Google Scholar
- Andrews, D., Sass, R., Anderson, E., Agron, J., Peck, W., Stevens, J., Baijot, F., and Komp, E. 2008. Achieving programming model abstractions for reconfigurable computing. IEEE Trans. VLSI Syst. 16, 4, 34--44. Google Scholar
Digital Library
- Banerjee, S., Bozorgzadeh, E., and Dutt, N. D. 2006. Integrating physical constraints in hw-sw partitioning for architectures with partial dynamic reconfiguration. IEEE Trans. VLSI Syst. 14, 11. Google Scholar
Digital Library
- Bazargan, K., Kastner, R., and Sarrafzadeh, M. 2000. Fast template placement for reconfigurable computing systems. IEEE Des. Test Comput. 17, 1, 68--83. Google Scholar
Digital Library
- Chen, Y.-H. and Hsiung, P.-A. 2005. Hardware task scheduling and placement in operating systems for dynamically reconfigurable SoC. In Proceedings of the 2005 IFIP International Conference on Embedded and Ubiquitous Computing (EUC’05). Lecture Notes in Computer Science, vol. 3824. Springer Verlag, 489--498. Google Scholar
Digital Library
- Corbetta, S., Ferrandi, F., Morandi, M., Santambrogio, M., and Sciuto, D. 2007. Two novel approaches to online partial bitstream relocation in a dynamically reconfigurable system. In Proceedings of the Annual Symposium on VLSI. IEEE Computer Society Press. Google Scholar
Digital Library
- Danne, K. and Platzner, M. 2005. Periodic real-time scheduling for FPGA computers. In Proceedings of the 3rd International Workshop on Intelligent Solutions in Embedded Systems (WISES’05). IEEE Computer Society, 117--127.Google Scholar
- ElFarag, A. A., El-Boghdadi, H. M., and Shaheen, S. I. 2007. Miss ratio improvement for real-time applications using fragmentation-aware placement. In Proceedings of the IEEE International Parallel and Distributed Processing Symposium.Google Scholar
- Handa, M. and Vemuri, R. 2004. An efficient algorithm for finding empty space for online FPGA placement. In Proceedings of the 41st Design Automation Conference (DAC’04). ACM Press, 960--965. Google Scholar
Digital Library
- Horta, E. and Lockwood, J. W. 2001. Parbit: A tool to transform bitfiles to implement partial reconfiguration of field programmable gate arrays (FPGAs). Tech. rep. WUCS-01-13, Washington University.Google Scholar
- Hsiung, P.-A. and Liu, C.-W. 2007. Exploiting hardware and software low power techniques for energy efficient co-scheduling in dynamically reconfigurable systems. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL’07). IEEE Computer Society Press, 165--170.Google Scholar
- Huang, C.-H., Chang, S.-S., and Hsiung, P.-A. 2007. Generic wrapper design for dynamic swappable hardware IP in partially reconfigurable systems. Int. J. Elect. Engin. 14, 3, 229--238.Google Scholar
- Huang, C.-H. and Hsiung, P.-A. 2008. Software-controlled dynamically swappable hardware design in partially reconfigurable systems. EURASIP J. Embed. Syst. 231940. Google Scholar
Digital Library
- Koch, D., Haubelt, C., Streichert, T., and Teich, J. 2007. Modeling and sythesis of hardware-software morphing. In Proceedings of the IEEE International Symposium on Circuits and Systems. 2746--2749.Google Scholar
- Liao, H.-W. 2007. Multi-objective placement of reconfigurable hardware tasks in real-time systems. M.S. thesis, National Chung Cheng University, Chiayi, Taiwan.Google Scholar
- Loo, S. M. and Wells, B. E. 2005. Task scheduling in a finite-resource, reconfigurable hardware/software codesign environment. INFORMS J. Comput. 18, 2, 151--172. Google Scholar
Digital Library
- Mei, B., Schaumont, P., and Vernalde, S. 2000. A hardware-software partitioning and scheduling algorithm for dynamically reconfigurable embedded systems. In Proceedings of the 11th ProRISC Workshop on Circuits, Systems and Signal Processing.Google Scholar
- Morandi, M., Novati, M., Santambrogio, M., and Sciuto, D. 2008. Core allocation and relocation management for a self dynamically reconfigurable architecture. In Proceedings of the Annual Symposium on VLSI. IEEE Computer Society Press, 286--291. Google Scholar
Digital Library
- Peck, W., Anderson, E., Agron, J., Stevens, J., Baijot, F., and Andrews, D. 2006. Hthreads: A computational model for reconfigurable devices. In Proceedings of the International Conference on Field Programmable Logic and Applications. 885--888.Google Scholar
- Pellizzoni, R. and Caccamo, M. 2006. Adaptive allocation of software and hardware real-time tasks for FPGA-based embedded systems. In Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS’06). IEEE Computer Society Press, 208--220. Google Scholar
Digital Library
- Porrmann, M., Kalte, H. G. L., and Rückert, U. 2005. Replica: A bitstream manipulation filter for module relocation in partial reconfigurable systems. In Proceedings of the 12th Reconfigurable Architectures Workshop. Google Scholar
Digital Library
- Steiger, C., Walder, H., Platzner, M., and Thiele, L. 2003. Online scheduling and placement of real-time tasks to partially reconfigurable devices. In Proceedings of the 24th IEEE International Real-Time Systems Symposium. IEEE Computer Society Press. Google Scholar
Digital Library
- Steiger, C., Walder, H., and Platzner, M. 2004. Operating systems for reconfigurable embedded platforms: Online scheduling of real-time tasks. IEEE Trans. Comput. 53, 11, 1393--1407. Google Scholar
Digital Library
- Tabero, J., Septien, J., Mecha, H., and Mozos, D. 2004. A low fragmentation heuristic for task placement in 2D RTR HW management. In Proceedings of the International Conference on Field-Programmable Logic and Applications. Springer Verlag, 241--250.Google Scholar
- Walder, H. and Platzner, M. 2003. Online scheduling for block-partitioned reconfigurable devices. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE). IEEE Computer Society, 10290--10295. Google Scholar
Digital Library
- Walder, H., Steiger, C., and Platzner, M. 2003. Fast online task placement on FPGAs: Free space partitioning and 2d-hashing. In Proceedings of the International Parallel and Distributed Processing Symposium. Vol. 17. IEEE Computer Society Press. Google Scholar
Digital Library
Index Terms
Scheduling and Placement of Hardware/Software Real-Time Relocatable Tasks in Dynamically Partially Reconfigurable Systems
Recommendations
Virtualizable hardware/software design infrastructure for dynamically partially reconfigurable systems
Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)In most existing works, reconfigurable hardware modules are still managed as conventional hardware devices. Further, the software reconfiguration overhead incurred by loading corresponding device drivers into the kernel of an operating system has been ...
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs
As technology continues to shrink, reducing leakage power of Field-Programmable Gate Arrays (FPGAs) becomes a critical issue for the practical use of FPGAs. In this article, we address the leakage issue of partially dynamically reconfigurable FPGA ...
Efficient On-line Hardware/Software Task Scheduling for Dynamic Run-time Reconfigurable Systems
IPDPSW '12: Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD ForumModern reconfigurable devices such as FPGAs can be reconfigured at run time. Some of them can be dynamically partially reconfigured, which means part of the FPGA is changed without interrupting other parts. This feature adds tremendous flexibility to ...






Comments