Abstract
Data caches are an increasingly important architectural feature in most modern computer systems. They help bridge the gap between processor speeds and memory access times. One inherent difficulty of using data caches in a real-time system is the unpredictability of memory accesses, which makes it difficult to calculate worst-case execution times (WCETs) of real-time tasks.
While cache analysis for single real-time tasks has been the focus of much research in the past, bounding the preemption delay in a multitask preemptive environment is a challenging problem, particularly for data caches.
This article makes multiple contributions in the context of independent, periodic tasks with deadlines less than or equal to their periods executing on a single processor.
1) For every task, we derive data cache reference patterns for all scalar and nonscalar references. These patterns are used to derive an upper bound on the WCET of real-time tasks.
2) We show that, when considering cache preemption effects, the critical instant does not occur upon simultaneous release of all tasks. We provide results for task sets with phase differences to prove our claim.
3) We develop a method to calculate tight upper bounds on the maximum number of possible preemptions for each job of a task and, considering the worst-case placement of these preemption points, derive a much tighter bound on its WCET. We provide results using both static-and dynamic-priority schemes.
Our results show significant improvements in the bounds derived. We achieve up to an order of magnitude improvement over two prior methods and up to half an order of magnitude over a third prior method for the number of preemptions, the WCET and the response time of a task. Consideration of the best-case and worst-case execution times of higher-priority jobs enables these improvements.
- Audsley, A. N., Burns, A., Richardson, M., and Tindell, K. 1993. Applying new scheduling theory to static priority pre-emptive scheduling. Softw. Eng. J., 284--292.Google Scholar
Cross Ref
- Basumallick, S. and Nilsen, K. 1994. Cache issues in real-time systems. In Proceedings of the Workshop on Language, Compiler, and Tool Support for Real-Time Systems. ACM, New York.Google Scholar
- Burger, D., Austin, T., and Bennett, S. 1996. Evaluating future microprocessors: The simplescalar toolset. Tech. rep. CS-TR-96-1308, University of Wisconsin, Madison, CS Dept. July.Google Scholar
- Busquets-Mataix, J. V. 1996. Adding instruction cache effect to an exact schedulability analysis of preemptive real-time systems. In Proceedings of the Euro-Micro Workshop on Real-Time Systems. IEEE, Los Alamitos, CA.Google Scholar
Cross Ref
- Chatterjee, S., Parker, E., Hanlon, P., and Lebeck, A. 2001. Exact analysis of the cache behavior of nested loops. In Proceedings of the Conference on Programming Language Design and Implementation. ACM, New York, 286--297. Google Scholar
Digital Library
- Fraguela, B. B., Doallo, R., and Zapata, E. L. 1999. Automatic analytical modeling for the estimation of cache misses. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques. IEEE, Los Alamitos, CA. Google Scholar
Digital Library
- Ghosh, S., Martonosi, M., and Malik, S. 1997. Cache miss equations: An analytical representation of cache misses. In Proceedings of the International Conference on Super-Computing. ACM, New York, 317--324. Google Scholar
Digital Library
- Ghosh, S., Martonosi, M., and Malik, S. 1999. Cache miss equations: A compiler framework for analyzing and tuning memory behavior. ACM Trans. Program. Lang. Syst. 21, 4, 703--746. Google Scholar
Digital Library
- Ju, L., Chakraborty, S., and Roychoudhury, A. 2007. Accounting for cache-related preemption delay in dynamic priority schedulability analysis. In Proceedings of the Design Automation and Test in Europe. IEEE, Los Alamitos, CA. Google Scholar
Digital Library
- Kim, S., Min, S., and Ha, R. 1996. Efficient worst case timing analysis of data caching. In Proceedings of the Real-Time Embedded Technology and Applications Symposium. IEEE, Los Alamitos, CA. Google Scholar
Digital Library
- Lee, C.-G., Hahn, J., Seo, Y.-M., Min, S. L., Ha, R., Hong, S., Park, C. Y., Lee, M., and Kim, C. S. 1998. Analysis or cache-related preemption delay in fixed-priority preemptive scheduling. IEEE Trans. Comput. 47, 6, 700--713. Google Scholar
Digital Library
- Lee, C.-G., Lee, K., Hahn, J., Seo, Y.-M., Min, S. L., Ha, R., Hong, S., Park, C. Y., Lee, M., and Kim, C. S. 2001. Bounding cache-related preemption delay for real-time systems. IEEE Trans. Softw. Eng. 27, 9, 805--826. Google Scholar
Digital Library
- Lehoczky, J., Sha, L., and Ding, Y. 1989. The rate monotonic scheduling algorithm: Exact characterization and average case behavior. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA.Google Scholar
- Li, Y.-T. S., Malik, S., and Wolfe, A. 1996. Cache modeling for real-time software: Beyond direct mapped instruction caches. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA, 254--263. Google Scholar
Digital Library
- Lim, S.-S., Bae, Y. H., Jang, G. T., Rhee, B.-D., Min, S. L., Park, C. Y., Shin, H., and Kim, C. S. 1994. An accurate worst-case timing analysis for RISC processors. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA, 97--108.Google Scholar
- Lisper, B. and Vera, X. 2003. Data cache locking for higher program predictability. In Proceeding of the International Conference on Measurement and Modeling of Computer Systems. ACM, New York, 272--282. Google Scholar
Digital Library
- Lundqvist, T. and Stenström, P. 1999. Empirical bounds on data caching in high-performance real-time systems. Tech. rep., Chalmers University of Technology.Google Scholar
- Negi, H. S., Mitra, T., and Roychoudhury, A. 2003. Accurate estimation of cache-related preemption delay. In Proceedings of the International Symposium on Hardware Software Co-Design. ACM, New York. Google Scholar
Digital Library
- Puaut, I. 2006. Wcet-centric software-controlled instruction caches for hard real-time systems. In Proceedings of the Euro-Micro Conference on Real-Time Systems. IEEE, Los Alamitos, CA. Google Scholar
Digital Library
- Puaut, I. and Decotigny, D. 2002. Low-complexity algorithms for static cache locking in multitasking hard real-time systems. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA. Google Scholar
Digital Library
- Ramaprasad, H. and Mueller, F. 2005. Bounding worst-case data cache behavior by analytically deriving cache reference patterns. In Proceedings of the Real-Time Embedded Technology and Applications Symposium. IEEE, Los Alamitos, CA, 148--157. Google Scholar
Digital Library
- Ramaprasad, H. and Mueller, F. 2006. Bounding preemption delay within data cache reference patterns for real-time tasks. In Proceedings of the Real-Time Embedded Technology and Applications Symposium. IEEE, Los Alamitos, CA, 71--80. Google Scholar
Digital Library
- Ramaprasad, H. and Mueller, F. 2007. Bounding worst-case response time for tasks with non-preemptive regions. Tech. rep. TR 2007-22, Dept. of Computer Science, North Carolina State University.Google Scholar
- Staschulat, J. and Ernst, R. 2004. Multiple process execution in cache related preemption delay analysis. In Proceedings of the International Conference on Embedded Software. ACM, New York. Google Scholar
Digital Library
- Staschulat, J. and Ernst, R. 2006. Worst-case timing analysis of input dependent data cache behavior. In Proceedings of the Euro-Micro Conference on Real-Time Systems. IEEE, Los Alamitos, CA. Google Scholar
Digital Library
- Staschulat, J., Schliecker, S., and Ernst, R. 2005. Scheduling analysis of real-time systems with precise modeling of cache related preemption delay. In Proceedings of the Euro-Micro Conference on Real-Time Systems. IEEE, Los Alamitos, CA. Google Scholar
Digital Library
- Tomiyama, H. and Dutt, N. D. 2000. Program path analysis to bound cache-related preemption delay in preemptive real-time systems. In Proceedings of the International Symposium on Hardware Software Co-Design. ACM, New York. Google Scholar
Digital Library
- Vera, X., Llosa, J., González, A., and Bermudo, N. 2000. A fast and accurate approach to analyze cache memory behavior (research note). In Proceedings of the 16th International Euro-Par Conference. Springer, Berlin, 194--198. Google Scholar
Digital Library
- Vera, X. and Xue, J. 2002. Let's study whole-program cache behavior analytically. In Proceedings of the International Symposium on High-Performance Computer Architecture. IEEE, Los Alamitos, CA. Google Scholar
Digital Library
- Wegener, J. and Mueller, F. 2001. A comparison of static analysis and evolutionary testing for the verification of timing constraints. Real-Time Syst. 21, 3, 241--268. Google Scholar
Digital Library
- White, R. T., Mueller, F., Healy, C., Whalley, D., and Harmon, M. G. 1999. Timing analysis for data and wrap-around fill caches. Real-Time Syst. 17, 2/3, 209--233. Google Scholar
Digital Library
- Zivojnovic, V., Velarde, J., Schlager, C., and Meyr, H. 1994. Dspstone: A dsp-oriented benchmarking methodology. In Proceedings of the International Conference on Signal Processing Applications and Technology.Google Scholar
Index Terms
Tightening the bounds on feasible preemptions
Recommendations
Tightening the Bounds on Feasible Preemption Points
RTSS '06: Proceedings of the 27th IEEE International Real-Time Systems SymposiumCaches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timing predictability of single real-time tasks has been the focus of much ...
Resilience analysis: tightening the CRPD bound for set-associative caches
LCTES '10: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systemsIn preemptive real-time systems, scheduling analyses need - in addition to the worst-case execution time - the context-switch cost. In case of preemption, the preempted and the preempting task may interfere on the cache memory.
This interference leads ...
Resilience analysis: tightening the CRPD bound for set-associative caches
LCTES '10In preemptive real-time systems, scheduling analyses need - in addition to the worst-case execution time - the context-switch cost. In case of preemption, the preempted and the preempting task may interfere on the cache memory.
This interference leads ...






Comments