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The architecture of the hardware unification unit and an implementation

Published:01 December 1985Publication History
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Abstract

This paper describes the architecture and the current implementation of the hardware unification unit (HUU). The HUU performs the literal unification operation in Prolog processing. It is designed as a coprocessor to a host system that handles other operations of Prolog processing such as bookkeeping and sequencing. After the host system provides input values to the HUU and activates it, the HUU works independently from the host system; when it finishes its operation it reports the result to the host system. The HUU contains local memory that stores the variable binding information. The microinstructions and a sample microprogram of the HUU are described. Performance measures obtained from the HUU simulator are presented and discussed.

References

  1. 1 N.S.Woq, "The Performance of the Bottleneck Function of a Prolog Processor," Technical Memo, AT&T Bell Lab. 1984.Google ScholarGoogle Scholar
  2. 2 T.P.Dobry, A.M.Despain, Y.N.Patt, "Performance Studies of a Prolog Machine Architecture," Proc. of the 12th Symposium on Computer Architecture, pp. 180-190, June 1985. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. 3 C. Sammut, UNSW Prolog User Manual, 1983.Google ScholarGoogle Scholar
  4. 4 N.S.Woo, "A Hardware Unification Unit: Design and Analysis," Proc. of the 12th Symposium on Computer Architecture, pp.l98-205, June 1985. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. 5 P.Robinson, "The SUM: An AI Coprocessor," Byte, pp.169.180, June 1985.Google ScholarGoogle Scholar
  6. 6 N.J.Nilsson, Principles of Artificial Intelligence, Tioga. Publishing Co. 1980. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. 7 N.Ito, et al., "Data-flow Based Execution Mechanisms of Parallel and Concurrent Prolog." New Generation Computing, 3, pp.15-41, 1985.Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. 8 K. Murakami, et al., "Research on Parallel Machine Architecture for Fifth-Generation Computer Systems," Computer, 18, 6, June 1985, pp. 76-92.Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. 9 N. Woo. "Incorporatin the Hardware Unification Unit to Prolog Machines," being prepared.Google ScholarGoogle Scholar
  10. 10 G. Sabbatel, et al., "Unification for a Prolog Data Base Machine," Proc. of the 2nd International Logic Programming Conference, pp.207-217, July 1984.Google ScholarGoogle Scholar

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            • Published in

              cover image ACM SIGMICRO Newsletter
              ACM SIGMICRO Newsletter  Volume 16, Issue 4
              Dec. 1985
              166 pages
              ISSN:1050-916X
              DOI:10.1145/18906
              Issue’s Table of Contents
              • cover image ACM Conferences
                MICRO 18: Proceedings of the 18th annual workshop on Microprogramming
                December 1985
                201 pages
                ISBN:0897911725
                DOI:10.1145/18927

              Copyright © 1985 Author

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              Association for Computing Machinery

              New York, NY, United States

              Publication History

              • Published: 1 December 1985

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