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HPS, a new microarchitecture: rationale and introduction

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Published:01 December 1985Publication History
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Abstract

HPS (High Performance Substrate) is a new microarchitecture targeted for implementing very high performance computing engines. Our model of execution is a restriction on fine granularity data flow. This paper introduces the model, provides the rationale for its selection, and describes the data path and flow of instructions through the microengine.

References

  1. 1 Anderson, D. W., Sparacio, F. J., Tomasulo, R. M., "The IBM Systed360 Model 91: Machine Philosophy and Instruction - Handling," IBM Journal of Research and Development, Vol. 11, No. 1, 1967, pp. 8-24.Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. 2 Arvind and Goostelow, K. P., "A New Interpreter for Dataflow and Its Implications for Computer Architecture," Department of Information and Computer Science, University of California, Irvine, Tech. Report 72, October 1975.Google ScholarGoogle Scholar
  3. 3 Dennis, J. B., and Misunas, D. P., "A Preliminary Architecture for a Basic Data Flow Processor," Proceedings of the Second International Symposium on Computer Architecture, 1975, pp 126-132. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. 4 Gajski, D., Kuck, D., Lawrie, D., Sameh, A., "CEDAR -- A Large Scale Multiprocessor," Computer Architecture News, March 1983. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. 5 Keller, R. M., "Look Ahead Processors," Computing Surveys, vol. 7, no. 4, Dec. 1975. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. 6 Tomasulo, R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal of Research and Development, vol. 11, 1967, pp 25 - 33. Principles and Examples, McGraw-Hill, 1982.Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. 7 Patt, Y.N., Melvin, SW., Hwu, W., and Shebanow, MC., "Critical Issues Regarding HPS, a High Performance Microarchitecture, Proceedings of the 18th International Microprogramming Workshop, Asilomar, CA, December, 1985. Google ScholarGoogle ScholarDigital LibraryDigital Library

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            • Published in

              cover image ACM SIGMICRO Newsletter
              ACM SIGMICRO Newsletter  Volume 16, Issue 4
              Dec. 1985
              166 pages
              ISSN:1050-916X
              DOI:10.1145/18906
              Issue’s Table of Contents
              • cover image ACM Conferences
                MICRO 18: Proceedings of the 18th annual workshop on Microprogramming
                December 1985
                201 pages
                ISBN:0897911725
                DOI:10.1145/18927

              Copyright © 1985 Authors

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              Association for Computing Machinery

              New York, NY, United States

              Publication History

              • Published: 1 December 1985

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