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Critical issues regarding HPS, a high performance microarchitecture

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Published:01 December 1985Publication History
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Abstract

HPS is a new model for a high performance microarchitecture which is targeted for implementing very dissimilar ISP architectures. It derives its performance from executing the operations within a restricted window of a program out-of-order, asynchronously, and concurrently whenever possible. Before the model can be reduced to an effective working implementation of a particular target architecture, several issues need to be resolved. This paper discusses these issues, both in general and in the context of architectures with specific characteristics.

References

  1. 1 Patt, Yale N., Hwu, Wen-mei, and Shebanow, Michael C., "HPS, a New Microarchitecture: Rationale and Introduction," The 18th Internoaional Microprogramming Workshop, Asilomsr, CA, December 1883. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. 2 Tomasulo, R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal of Rceearch and Development, vol. 11, 1967, pp, 25-33.Google ScholarGoogle ScholarDigital LibraryDigital Library

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              • Published in

                cover image ACM SIGMICRO Newsletter
                ACM SIGMICRO Newsletter  Volume 16, Issue 4
                Dec. 1985
                166 pages
                ISSN:1050-916X
                DOI:10.1145/18906
                Issue’s Table of Contents
                • cover image ACM Conferences
                  MICRO 18: Proceedings of the 18th annual workshop on Microprogramming
                  December 1985
                  201 pages
                  ISBN:0897911725
                  DOI:10.1145/18927

                Copyright © 1985 Authors

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                Association for Computing Machinery

                New York, NY, United States

                Publication History

                • Published: 1 December 1985

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