Abstract
HPS is a new model for a high performance microarchitecture which is targeted for implementing very dissimilar ISP architectures. It derives its performance from executing the operations within a restricted window of a program out-of-order, asynchronously, and concurrently whenever possible. Before the model can be reduced to an effective working implementation of a particular target architecture, several issues need to be resolved. This paper discusses these issues, both in general and in the context of architectures with specific characteristics.
- 1 Patt, Yale N., Hwu, Wen-mei, and Shebanow, Michael C., "HPS, a New Microarchitecture: Rationale and Introduction," The 18th Internoaional Microprogramming Workshop, Asilomsr, CA, December 1883. Google Scholar
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- 2 Tomasulo, R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal of Rceearch and Development, vol. 11, 1967, pp, 25-33.Google Scholar
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Index Terms
Critical issues regarding HPS, a high performance microarchitecture
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