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Hardware acceleration of logic simulation using a data flow microarchitecture

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Published:01 December 1985Publication History
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Abstract

Current digital logic simulators running on engineering workstations lack capacity and speed. This paper discusses a hardware accelerator for a workstation simulator which addresses these problems. The accelerator runs 100x faster than its software counterpart and can simulate up to 1 million gates. The accelerator has been built and is being sold commercially. The architecture of the accelerator is similar to that of a classical dataflow machine. We describe the architecture of the machine and illustrate how it would simulate a simple circuit. We then briefly discuss the relationship between event driven simulation and dataflow.

References

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  1. Hardware acceleration of logic simulation using a data flow microarchitecture

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        • Published in

          cover image ACM SIGMICRO Newsletter
          ACM SIGMICRO Newsletter  Volume 16, Issue 4
          Dec. 1985
          166 pages
          ISSN:1050-916X
          DOI:10.1145/18906
          Issue’s Table of Contents
          • cover image ACM Conferences
            MICRO 18: Proceedings of the 18th annual workshop on Microprogramming
            December 1985
            201 pages
            ISBN:0897911725
            DOI:10.1145/18927

          Copyright © 1985 Authors

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          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 1 December 1985

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