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JAM—just another microsequencer

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Published:01 December 1985Publication History
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Abstract

JAM (Just Another Microsequencer) is a flexible - dual role microcode sequencer. It supports high performance N-Way microsequencing operations (traditional 360/370 type branch address generation techniques), along with more traditional (a la AMD 2910) sequencing control over “structured” microcode. A unique feature of the chip is that the degree of parallel branching can be changed dynamically. That is, the chip can be reconfigured to support 2-way, 4-way, … up to 256-way branching on a 14 bit Control Store address.

There are 16 microsequencing operations supported including:

  • Next Sequential Control Store Address

  • N-Way Branch, N-Way Call and N-Way Return (Including several submodes)

  • Conditional Branch, Conditional Call and Conditional Return

  • Loop Control

An on-chip stack provides micro-routine nesting up to 8 levels deep. The stack is also used for looping and a special conditional branching mechanism. The chip has been designed and fabricated using 4 micron NMOS technology and has a cycle time of under 100 nanoseconds.

References

  1. 1 Advanced Micro Devices, Bipolar Microprocessor m and Interface Data Book 1983.]]Google ScholarGoogle Scholar
  2. 2 Fisher, Joseph A., "Two to the N-Way Jump Microinstruction Hardware and an Effective Instruction Binding", Proceedings of the 14th Annual Workshop on Microprogramming, ACM, November, 1980.]] Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. 3 Hennessey, John, "Stanford Language for Implementing Microcode", SIGMICRO Newsletter Vol. 16, No. 2 (July), 1985]] Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. 4 Husson, S., Microprogramming: Principles and Practices, Prentice Hall, 1970.]]Google ScholarGoogle Scholar
  5. 5 Jones, Louise H., "The Role of Instruction Sequencing In Structured Microprogramming", Preprints, Micro 7, September 1974, pp. 277-278.]] Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. 6 Jouppi, Norman P., "Timing Verification and Performance Improvement of MOS VLSI Designs", PhD Thesis Stanford University 1984.]]Google ScholarGoogle Scholar
  7. 7 Mead, Carver and Conway, Lynn, Introduction to VLSI Systems Addison-Wesley 1980.]] Google ScholarGoogle ScholarDigital LibraryDigital Library

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              • Published in

                cover image ACM SIGMICRO Newsletter
                ACM SIGMICRO Newsletter  Volume 16, Issue 4
                Dec. 1985
                166 pages
                ISSN:1050-916X
                DOI:10.1145/18906
                Issue’s Table of Contents
                • cover image ACM Conferences
                  MICRO 18: Proceedings of the 18th annual workshop on Microprogramming
                  December 1985
                  201 pages
                  ISBN:0897911725
                  DOI:10.1145/18927

                Copyright © 1985 Authors

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                Association for Computing Machinery

                New York, NY, United States

                Publication History

                • Published: 1 December 1985

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