Abstract
JAM (Just Another Microsequencer) is a flexible - dual role microcode sequencer. It supports high performance N-Way microsequencing operations (traditional 360/370 type branch address generation techniques), along with more traditional (a la AMD 2910) sequencing control over “structured” microcode. A unique feature of the chip is that the degree of parallel branching can be changed dynamically. That is, the chip can be reconfigured to support 2-way, 4-way, … up to 256-way branching on a 14 bit Control Store address.
There are 16 microsequencing operations supported including:
Next Sequential Control Store Address
N-Way Branch, N-Way Call and N-Way Return (Including several submodes)
Conditional Branch, Conditional Call and Conditional Return
Loop Control
An on-chip stack provides micro-routine nesting up to 8 levels deep. The stack is also used for looping and a special conditional branching mechanism. The chip has been designed and fabricated using 4 micron NMOS technology and has a cycle time of under 100 nanoseconds.
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Digital Library
- 3 Hennessey, John, "Stanford Language for Implementing Microcode", SIGMICRO Newsletter Vol. 16, No. 2 (July), 1985]] Google Scholar
Digital Library
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Digital Library
- 6 Jouppi, Norman P., "Timing Verification and Performance Improvement of MOS VLSI Designs", PhD Thesis Stanford University 1984.]]Google Scholar
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Digital Library
Index Terms
JAM—just another microsequencer
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