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Reprogrammable hardware for educational purposes

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Published:12 March 1994Publication History
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Abstract

This paper presents a novel idea in teaching computer architecture by using programmable hardware. Current teaching models for computer architecture today are either mostly theory-only or implementation oriented. Theory-based architecture courses lack the feedback to show students the effects of their decisions. Implementation-oriented instruction emphasizes the implementation aspects, that is, very low-level implementation strategies, over CPU architecture and forces the usage of very limited CPU designs to reduce complexity. High cost and long manufacturing times are other problems associated with this approach.

We propose to use field programmable gate arrays (FPGAs) to allow fast implementation of chip designs. This allows for a fast debug cycle, as designs can be altered and downloaded in a matter of hours. As FPGAs are pretested, only logic functionality has to be validated, reducing the time to get a workable implementation of a chip considerably.

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      • Published in

        cover image ACM SIGCSE Bulletin
        ACM SIGCSE Bulletin  Volume 26, Issue 1
        March 1994
        410 pages
        ISSN:0097-8418
        DOI:10.1145/191033
        Issue’s Table of Contents
        • cover image ACM Conferences
          SIGCSE '94: Proceedings of the twenty-fifth SIGCSE symposium on Computer science education
          March 1994
          414 pages
          ISBN:0897916468
          DOI:10.1145/191029

        Copyright © 1994 ACM

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 12 March 1994

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