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The reduceron reconfigured

Published:27 September 2010Publication History
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Abstract

The leading implementations of graph reduction all target conventional processors designed for low-level imperative execution. In this paper, we present a processor specially designed to perform graph-reduction. Our processor -- the Reduceron -- is implemented using off-the-shelf reconfigurable hardware. We highlight the low-level parallelism present in sequential graph reduction, and show how parallel memories and dynamic analyses are used in the Reduceron to achieve an average reduction rate of 0.55 function applications per clock-cycle.

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References

  1. }}L. Augustsson. BWM: A Concrete Machine for Graph Reduction. In Proceedings of the 1991 Glasgow Workshop on Functional Programming, pages 36--50, Springer, 1992. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. }}G. L. Burn, S. L. Peyton Jones and J. D. Robson. The Spineless G-machine. In Proceedings of the 1988 Conference on Lisp and Functional Programming, pages 244--258, ACM, 1988. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. }}C. Clack. Realisations for non-strict languages. In Research Directions in Parallel Functional Programming, pages 149--187. Springer, 1999.Google ScholarGoogle ScholarCross RefCross Ref
  4. }}E. W. Dijkstra. A mild variant of Combinatory Logic. EWD735, 1980.Google ScholarGoogle Scholar
  5. }}J. H. Fasel and R. M. Keller, editors. Graph Reduction, Proceedings of a Workshop. Springer LNCS 279, 1987.Google ScholarGoogle Scholar
  6. }}C. Flanagan, A. Sabry, and B. F. Duba, and M. Felleisen. The essence of compiling with continuations. In PLDI '93: Proceedings of the ACM SIGPLAN 1993 Conference on Programming Language Design and Implementation, pages 237--247, ACM, 1993. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. }}A. Gill and G. Hutton. The Worker/Wrapper Transformation. JFP, volume 18, part 2, pages 227--251, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. }}J. Hennessy and D. Patterson. Computer Architecture; A Quantitative Approach. Morgan Kaufmann, 1992. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. }}J. M. Jansen, P. Koopman, R. Plasmeijer. Efficient Interpretation by Transforming Data Types and Patterns to Functions. In Trends in Functional Programming, volume 7, pages 157--172, 2007.Google ScholarGoogle Scholar
  10. }}R. Jones and R. Lins. Garbage Collection: Algorithms for Automatic Dynamic Memory Management. Wiley, 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. }}R. Kennaway and R. Sleep. Director strings as combinators. ACM Transactions on Programming Languages and Systems, volume 10, number 4, pages 602--626, 1988. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. }}R. Longbottom. Dhrystone Benchmark Results On PCs, November 2009.Google ScholarGoogle Scholar
  13. }}(http://www.roylongbottom.org.uk/dhrystone%20results.htm.Google ScholarGoogle Scholar
  14. }}M. Naylor and C. Runciman. The Reduceron: Widening the von Neumann bottleneck for graph reduction using an FPGA. In IFL'07, pages 129--146. Springer LNCS 5083, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. }}M. Naylor, C. Runciman, and J. Reich. Reduceron home page. (http://www.cs.york.ac.uk/fp/reduceron/.Google ScholarGoogle Scholar
  16. }}M. Naylor. F-lite: a core subset of Haskell, 2008. (http://www.cs.york.ac.uk/fp/reduceron/memos/Memo9.txt.Google ScholarGoogle Scholar
  17. }}M. Naylor. An algorithm for arity-reduction, 2008. (http://www.cs.york.ac.uk/fp/reduceron/memos/Memo12.lhs.Google ScholarGoogle Scholar
  18. }}M. Naylor. Design of the Octostack, 2009. (http://www.cs.york.ac.uk/fp/reduceron/memos/Memo27.lhs.Google ScholarGoogle Scholar
  19. }}Xilinx. MicroBlaze Soft Processor v7.20, April 2009.Google ScholarGoogle Scholar
  20. }}(\url{http://www.xilinx.com/tools/microblaze.htm}.Google ScholarGoogle Scholar
  21. }}S. L. Peyton Jones. The Implementation of Functional Programming Languages, Prentice Hall, 1987. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. }}S. L. Peyton Jones. Implementing lazy functional languages on stock hardware: the Spineless Tagless G-machine. Journal of Functional Programming, volume 2, pages 127--202, 1992.Google ScholarGoogle Scholar
  23. }}M. Scheevel. NORMA: a graph reduction processor. In Proceedings of the 1986 Conference on LISP and Functional Programming, pages 212--219. ACM, 1986. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. }}W. Stoye. The Implementation of Functional Languages using Custom Hardware. PhD Thesis, University of Cambridge, 1985.Google ScholarGoogle Scholar
  25. }}D. A. Turner. A New Implementation Technique for Applicative Languages. Software -- Practice and Experience, volume 9, number 1, pages 31--49, 1979.Google ScholarGoogle Scholar
  26. }}R. Weicker. Dhrystone: A Synthetic Systems Programming Benchmark. Communications of the ACM, volume 27, number 10, pages 1013--1030, 1984.. Google ScholarGoogle ScholarDigital LibraryDigital Library

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        • Published in

          cover image ACM SIGPLAN Notices
          ACM SIGPLAN Notices  Volume 45, Issue 9
          ICFP '10
          September 2010
          382 pages
          ISSN:0362-1340
          EISSN:1558-1160
          DOI:10.1145/1932681
          Issue’s Table of Contents
          • cover image ACM Conferences
            ICFP '10: Proceedings of the 15th ACM SIGPLAN international conference on Functional programming
            September 2010
            398 pages
            ISBN:9781605587943
            DOI:10.1145/1863543

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          • Published: 27 September 2010

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