skip to main content
10.1145/1950365.1950372acmconferencesArticle/Chapter ViewAbstractPublication PagesasplosConference Proceedingsconference-collections
research-article

Hardware acceleration of transactional memory on commodity systems

Published:05 March 2011Publication History

ABSTRACT

The adoption of transactional memory is hindered by the high overhead of software transactional memory and the intrusive design changes required by previously proposed TM hardware. We propose that hardware to accelerate software transactional memory (STM) can reside outside an unmodified commodity processor core, thereby substantially reducing implementation costs. This paper introduces Transactional Memory Acceleration using Commodity Cores (TMACC), a hardware-accelerated TM system that does not modify the processor, caches, or coherence protocol.

We present a complete hardware implementation of TMACC using a rapid prototyping platform. Using this hardware, we implement two unique conflict detection schemes which are accelerated using Bloom filters on an FPGA. These schemes employ novel techniques for tolerating the latency of fine-grained asynchronous communication with an out-of-core accelerator. We then conduct experiments to explore the feasibility of accelerating TM without modifying existing system hardware. We show that, for all but short transactions, it is not necessary to modify the processor to obtain substantial improvement in TM performance. In these cases, TMACC outperforms an STM by an average of 69% in applications using moderate-length transactions, showing maximum speedup within 8% of an upper bound on TM acceleration. Overall, we demonstrate that hardware can substantially accelerate the performance of an STM on unmodified commodity processors.

References

  1. A.-R. Adl-Tabatabai, B. Lewis, V. Menon, B. R. Murphy, B. Saha, and T. Shpeisman. Compiler and runtime support for efficient software transactional memory. In PLDI '06: ACM SIGPLAN Conference on Programming Language Design and Implementation, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. W. Baek, C. Cao Minh, M. Trautmann, C. Kozyrakis, and K. Olukotun. The Open™ transactional application programming interface. In PACT '07: 16th Internation Conference on Parallel Architecture and Compilation Techniques, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. B. Bloom. Space/time trade-offs in hash coding with allowable errors. Communications of ACM, 1970. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. C. Blundell, J. Devietti, E. C. Lewis, and M. M. K. Martin. Making the fast case common and the uncommon case simple in unbounded transactional memory. In ISCA '07: 34th International Symposium on Computer Architecture, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. J. Bobba, N. Goyal, M. Hill, M. Swift, and D. Wood. Tokentm: Efficient execution of large transactions with hardware transactional memory. In ISCA '08: 35th International Symposium on Computer Architecture, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. C. Cao Minh, J. Chung, C. Kozyrakis, and K. Olukotun. STAMP: Stanford transactional applications for multi-processing. In IISWC '08: Proc. The IEEE International Symposium on Workload Characterization, 2008.Google ScholarGoogle Scholar
  7. C. Cao Minh, M. Trautmann, J. Chung, A. McDonald, N. Bronson, J. Casper, C. Kozyrakis, and K. Olukotun. An effective hybrid transactional memory system with strong isolation guarantees. In ISCA '07: 34th International Symposium on Computer Architecture, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. J. L. Carter and M. N. Wegman. Universal classes of hash functions. Journal of Computer and System Sciences, 18(2), 1979.Google ScholarGoogle ScholarCross RefCross Ref
  9. C. Cascaval, C. Blundell, M. Michael, H. W. Cain, P. Wu, S. Chiras, and S. Chatterjee. Software transactional memory: Why is it only a research toy? Queue, 6(5), 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. L. Ceze, J. Tuck, P. Montesinos, and J. Torrellas. BulkSC: bulk enforcement of sequential consistency. In ISCA '07: 34th International Symposium on Computer architecture, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. H. Chafi, J. Casper, B. D. Carlstrom, A. McDonald, C. Cao Minh, W. Baek, C. Kozyrakis, and K. Olukotun. A scalable, non-blocking approach to transactional memory. In HPCA '07: 13th International Symposium on High Performance Computer Architecture, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. S. Chaudhry, R. Cypher, M. Ekman, M. Karlsson, A. Landin, S. Yip, H. Zeffer, and M. Tremblay. Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor. In ISCA '09: 36th Intl. Symposium on Computer Architecture, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. L. Dalessandro, M. F. Spear, and M. L. Scott. NOrec: streamlining S™ by abolishing ownership records. In PPoPP '10: 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP '10, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. P. Damron, A. Fedorova, Y. Lev, V. Luchangco, M. Moir, and D. Nussbaum. Hybrid transactional memory. In ASPLOS '06: 12th Internation Conference on Architectural Support for Programming Languages and Operating Systems, October 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. D. Dice, O. Shalev, and N. Shavit. Transactional locking II. In DISC '06: 20th Internation Symposium on Distributed Computing, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. A. Dragojević, R. Guerraoui, and M. Kapalka. Stretching transactional memory. In PLDI '09: ACM SIGPLAN Conference on Programming Language Design and Implementation, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. L. Hammond, V. Wong, M. Chen, B. D. Carlstrom, J. D. Davis, B. Hertzberg, M. K. Prabhu, H. Wijaya, C. Kozyrakis, and K. Olukotun. Transactional memory coherence and consistency. In ISCA '04: 31st International Symposium on Computer Architecture, 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. T. Harris and K. Fraser. Language support for lightweight transactions. In OOPSLA '03: 18th ACM SIGPLAN Conference on Object-oriented Programing, Systems, Languages, and Applications, 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. M. Herlihy and J. E. B. Moss. Transactional memory: Architectural support for lock-free data structures. In ISCA '93: 20th International Symposium on Computer Architecture, 1993. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. O. S. Hofmann, C. J. Rossbach, and E. Witchel. Maximum benefit from a minimal H™. In ASPLOS '09: 14th International Conference on Architectural Support for Programming Languages and Operating Systems, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. S. Hong, T. Oguntebi, J. Casper, N. Bronson, C. Kozyrakis, and K. Olukotun. Eigenbench: A simple exploration tool for orthogonal tm characteristics. In IISWC '10: International Symposium on Workload Characterization, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. S. Kumar, M. Chu, C. J. Hughes, P. Kundu, and A. Nguyen. Hybrid transactional memory. In PPoPP '06: 11th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. J. Larus and R. Rajwar. Transactional Memory. Morgan Claypool Synthesis Series, 2006.Google ScholarGoogle Scholar
  24. M. Lupon, G. Magklis, and A. González. FAS™: A log-based hardware transactional memory with fast abort recovery. In PACT '09: 18th International Conference on Parallel Architecture and Compilation Techniques, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. V. J. Marathe, W. N. Scherer III, and M. L. Scott. Adaptive Software Transactional Memory. In DISC '05: 19th International Symposium on Distributed Computing, 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. S. S. Mukherjee, B. Falsafi, M. D. Hill, and D. A. Wood. Coherent network interfaces for fine-grain communication. In ISCA '96: 23rd International Symposium on Computer Architecture, 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. T. Oguntebi, S. Hong, J. Casper, N. Bronson, C. Kozyrakis, and K. Olukotun. FARM: A prototyping environment for tightly-coupled, heterogeneous architectures. In FCCM '10: 18th Symposium on Field-Programmable Custom Computing Machines, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. M. Olszewski, J. Cutler, and J. G. Steffan. JudoS™: A dynamic binary-rewriting approach to software transactional memory. In PACT '07: 16th International Conference on Parallel Architecture and Compilation Techniques. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. H. E. Ramadan, C. J. Rossbach, D. E. Porter, O. S. Hofmann, A. Bhandari, and E. Witchel. Metatm/txlinux: transactional memory for an operating system. SIGARCH Computer Architecture News, 35(2), 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. B. Saha, A. Adl-Tabatabai, and Q. Jacobson. Architectural support for software transactional memory. In MICRO '06: International Symposium on Microarchitecture, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. B. Saha, A.-R. Adl-Tabatabai, R. L. Hudson, C. Cao Minh, and B. Hertzberg. McRT-S™: A high performance software transactional memory system for a multi-core runtime. In PPoPP '06: 11th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. T. Shpeisman, V. Menon, A.-R. Adl-Tabatabai, S. Balensiefer, D. Grossman, R. L. Hudson, K. Moore, and B. Saha. Enforcing isolation and ordering in stm. In PLDI '07: Conference on Programming Language Design and Implementation, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. A. Shriraman, S. Dwarkadas, and M. L. Scott. Flexible decoupled transactional memory support. In ISCA '08: 35th International Symposium on Computer Architecture, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  34. A. Shriraman, M. F. Spear, H. Hossain, V. J. Marathe, S. Dwarkadas, and M. L. Scott. An integrated hardware-software approach to flexible transactional memory. SIGARCH Computer Architecture News, 35, June 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. M. F. Spear. Lightweight, robust adaptivity for software transactional memory. In SPAA '10: 22nd ACM Symposium on Parallelism in Algorithms and Architectures, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. M. F. Spear, M. M. Michael, and C. von Praun. RingS™: scalable transactions with a single atomic instruction. In SPAA '08: 20th Symposium on Parallelism in Algorithms and Architectures, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. STAMP: Stanford transactional applications for multi-processing. http://stamp.stanford.edu.Google ScholarGoogle Scholar
  38. F. Tabba, M. Moir, J. R. Goodman, A. Hay, and C. Wang. NZ™: Nonblocking zero-indirection transactional memory. In SPAA '09: 21st Symposium on Parallelism in Algorithms and Architectures, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  39. C. Wang, W.-Y. Chen, Y. Wu, B. Saha, and A.-R. Adl-Tabatabai. Code generation and optimization for transactional memory constructs in an unmanaged language. In CGO '07: International Symposium on Code Generation and Optimization, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  40. L. Yen, J. Bobba, M. R. Marty, K. E. Moore, H. Volos, M. D. Hill, M. M. Swift, and D. A. Wood. LogTM-SE: Decoupling Hardware Transactional Memory from Caches. In HPCA '07: 13th International Symposium on High Performance Computer Architecture, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  41. L. Yen, S. Draper, and M. Hill. Notary: Hardware techniques to enhance signatures. In MICRO '08: 41st International Symposium on Microarchitecture, 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Hardware acceleration of transactional memory on commodity systems

      Recommendations

      Comments

      Login options

      Check if you have access through your login credentials or your institution to get full access on this article.

      Sign in

      PDF Format

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader
      About Cookies On This Site

      We use cookies to ensure that we give you the best experience on our website.

      Learn more

      Got it!