Abstract
The VAX architecture is a popular ISP architecture that has been implemented in several different technologies targeted to a wide range of performance specifications. However, it has been argued that the VAX has specific characteristics which preclude a very high performance implementation. We have developed a microarchitecture (HPS) which is specifically intended for implementing very high performance computing engines. Our model of execution is a restriction on fine granularity data flow. In this paper, we concentrate on one particular aspect of an HPS implementation of the VAX architecture: the generation of HPS microinstructions (i.e. data flow nodes) from a VAX instruction stream.
- 1 Anderson, D. W., Sparacio, F. J., Tomasulo, R. M., "The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling," IBM Journal of Research and Development, vol. 11, January, 1967, pp. 8-24.Google Scholar
Digital Library
- 2 Patt, Yale N., Hwu, Wen-mei, and Shebanow, Michael C., "HPS, a New Microarchitecture: Rationale and Introduction," The 18th International Microprogramming Workshop, Asilomar, CA, December 1985. Google Scholar
Digital Library
- 3 Patt, Yale N., Melvin, Stephen W., Hwu, Wen-mei, Shebanow, Michael C., "Critical Issues Regarding HPS, A High Performance Microarchitecture," The 18th International Microprogramming Workshop, Asilomar, CA, December 1985. Google Scholar
Digital Library
- 4 Tomasulo, R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal of Research and Development, vol. 11, January, 1967, pp. 25-33.Google Scholar
Digital Library
- 5 VAX Architecture Handbook, Digital Equipment Corporation, 1981.Google Scholar
Index Terms
Run-time generation of HPS microinstructions from a VAX instruction stream
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Run-time generation of HPS microinstructions from a VAX instruction stream
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