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A case study in signal processing microprogramming using the URPR software pipelining technique

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Published:01 December 1986Publication History
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Abstract

There are a growing number of micro-architectures that employ pipelined array units for high-speed floating point applications. To obtain the performance required in such applications, effective loop optimization is crucial. The loop optimization problem for micro-architectures with pipelined processing units is similar to the problem of array processor loop optimization. The URPR method has been proven to be an effective, low-complexity approach to optimizing loops in array processor programs, so we conducted a case study of the method applied to a representative pipelined microarchitecture based on the AMD29500 chip family. The results of applying two URPR compaction algorithms and a new compaction algorithm to the 29500-based micro-architecture are presented. With the new compaction algorithm, we were able to realize microcode as efficient as the complex microcode manually derived by AMD.

References

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  1. A case study in signal processing microprogramming using the URPR software pipelining technique

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            • Published in

              cover image ACM SIGMICRO Newsletter
              ACM SIGMICRO Newsletter  Volume 17, Issue 4
              Dec. 1986
              163 pages
              ISSN:1050-916X
              DOI:10.1145/19530
              Issue’s Table of Contents
              • cover image ACM Conferences
                MICRO 19: Proceedings of the 19th annual workshop on Microprogramming
                December 1986
                179 pages
                ISBN:081860736X
                DOI:10.1145/19551

              Copyright © 1986 Authors

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              Association for Computing Machinery

              New York, NY, United States

              Publication History

              • Published: 1 December 1986

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