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A microcoded RISC

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Published:01 December 1986Publication History
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Abstract

A new, microcoded, RISC-type system is proposed and presented. The microcode is stored in a 256 x 64 PROM Nanomemory in the CPU. The 8-bit opcode of each instruction is a direct address to the Nanomemory. Each Nanomemory 64-bit word (horizontal microcode) corresponds to a specific machine language instruction. A large 2048 x 32 CPU Register file, using the register window approach, is implemented. A bit-sliced (AMD2900) prototype is currently under construction.

References

  1. 1 D.A. Patterson, Reduced Instruction Set Computers, Comm. ACM, Vol. 28, No. 1, pp. 8-21, Jan. 1985. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. 2 M.G.H. Katevenis, Reduced Instruction Set Computer Architectures for VLSI, MIT Press, Cambridge, MA, 1985. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. 3 D.P. Siewiorek, C.G. Bell, A. Newell, Computer Structures: Principles and Examples, McGraw Hill, NY, 1982. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. 4 W.A. Triebel, A. Singh, 16-Bit Microprocessors, Prentice-Hall, Englewood Cliffs, NJ, 1985.Google ScholarGoogle Scholar

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  1. A microcoded RISC

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            • Published in

              cover image ACM SIGMICRO Newsletter
              ACM SIGMICRO Newsletter  Volume 17, Issue 4
              Dec. 1986
              163 pages
              ISSN:1050-916X
              DOI:10.1145/19530
              Issue’s Table of Contents
              • cover image ACM Conferences
                MICRO 19: Proceedings of the 19th annual workshop on Microprogramming
                December 1986
                179 pages
                ISBN:081860736X
                DOI:10.1145/19551

              Copyright © 1986 Authors

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              Association for Computing Machinery

              New York, NY, United States

              Publication History

              • Published: 1 December 1986

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