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Exploring circuit timing-aware language and compilation

Published:05 March 2011Publication History
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Abstract

By adjusting the design of the ISA and enabling circuit timing-sensitive optimizations in a compiler, we can more effectively exploit timing speculation. While there has been growing interest in systems that leverage circuit-level timing speculation to improve the performance and power-efficiency of processors, most of the innovation has been at the microarchitectural level. We make the observation that some code sequences place greater demand on circuit timing deadlines than others. Furthermore, by selectively replacing these codes with instruction sequences which are semantically equivalent but reduce activity on timing critical circuit paths, we can trigger fewer timing errors and hence reduce recovery costs.

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      • Published in

        cover image ACM SIGPLAN Notices
        ACM SIGPLAN Notices  Volume 46, Issue 3
        ASPLOS '11
        March 2011
        407 pages
        ISSN:0362-1340
        EISSN:1558-1160
        DOI:10.1145/1961296
        Issue’s Table of Contents
        • cover image ACM Conferences
          ASPLOS XVI: Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
          March 2011
          432 pages
          ISBN:9781450302661
          DOI:10.1145/1950365

        Copyright © 2011 ACM

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        • Published: 5 March 2011

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