Abstract
Just-In-Time (JIT) compilation is frequently used in software engineering to accelerate program execution. Parts of the code are translated to machine code at runtime to speedup their execution by exploiting local and dynamic information of the computation. Modern FPGAs manufactured by Xilinx allow partial and dynamic configuration. Such features make them eligible platforms for JIT hardware compilation. Nevertheless, this has not been achieved until now because the mapping between a bitstream and the programmable points inside these FPGAs is not documented. In this article, we propose a methodology to retrieve the relevant information in logarithmic time per bit by methodically using the tools distributed by Xilinx. We give a practical case study which details the analysis of a Virtex-II Pro FPGA bitstream. The mapping of CLBs, BRAMs, and multipliers has been fully determined. Thanks to this information, we have been able to prototype tools in the fields of reverse mapping FPGA bitstreams, low-level simulation, and custom place-and-route. Finally preliminary results demonstrate that a processor embedded in an FPGA can compile, place, and route arithmetic and logic expressions inside the FPGA within a few milliseconds.
- Bala, V., Duesterwald, E., and Banerjia, S. 2000. Dynamo: A transparent dynamic optimisation System. Tech. rep., Hewlett-Packard Labs.Google Scholar
Digital Library
- Bellows, P. and Hutchings, B. 1998. JHDL - An HDL for reconfigurable systems. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines. K. L. Pocek and J. Arnold Eds., IEEE Computer Society Press, 175--184. Google Scholar
Digital Library
- Bergeron, E., Feeley, M., and David, J. P. 2007. Toward on-chip JIT synthesis on xilinx virtex-II pro FPGAs. In Proceedings of the 50th International Midwest Symposium on Circuits and Systems/5th International Northeast Workshop on Circuits (MWCAS/NEWCAS).Google Scholar
- Bergeron, E., Feeley, M., and David, J. P. 2008. Hardware JIT compilation for off-the-shelf dynamically reconfigurable FPGAs. In Compiler Construction, Lecture Notes in Computer Science, vol. 4959, Springer, 178--192. Google Scholar
Digital Library
- Betz, V. and Rose, J. 1997. VPR: A new packing, placement and routing tool for FPGA research. In Field-Programmable Logic and Applications, W. Luk, P. Y. Cheung, and M. Glesner Eds., Springer, Berlin, 213--222. Google Scholar
Digital Library
- Engler, D. R. and Hsieh, W. C. 2000. Derive: a tool that automatically reverse-engineers instruction encodings. SIGPLAN Not. 35, 12--22. Google Scholar
Digital Library
- Franklin, N. 2003. VirtexTools FPGA programming and debugging tools project. http://neil.franklin.ch/Projects/VirtexTools/.Google Scholar
- Guccione, S., Levi, D., and Sundararajan, P. 1999. JBits: A Java-based interface for reconfigurable computing. In Proceedings of the 2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD).Google Scholar
- Horta, E. and Lockwood, J. W. 2001. PARBIT: A tool to transform bitfiles to implement partial reconfiguration of field programmable gate arrays (FPGAs). Tech. rep. WUCS-01-13, Department of Computer Science, Washington University in Saint Louis.Google Scholar
- Hsieh, W. C., Engler, D. R., and Back, G. 2001. Reverse-Engineering instruction encodings. In Proceedings of the General Track 2002 USENIX Annual Technical Conference. USENIX Association, 133--145. Google Scholar
Digital Library
- Kelsey, R., Clinger, W., and (Editors), J. R. 1998. Revised<sup>5</sup> report on the algorithmic language scheme. ACM SIGPLAN Not. 33, 9, 26--76. Google Scholar
Digital Library
- Lim, D. and Peattie, M. 2002. Two flows for partial reconfigurable core based on small bit manipulations, XAPP290 (v1.0). Tech. rep., Xilinx.Google Scholar
- Lysecky, R., Vahid, F., and Tan, S. X.-D. 2004. Dynamic FPGA routing for just-in-time FPGA compilation. In Proceedings of the 41st Annual Conference on Design Automation (DAC’04). ACM, New York, 954--959. Google Scholar
Digital Library
- Lysecky, R., Stitt, G., and Vahid, F. 2006. Warp processors. ACM Trans. Des. Autom. Electron. Syst. 11, 3, 659--681. Google Scholar
Digital Library
- Note, J.-B. 2007. FPGA Netlist recovery. http://www.ulogic.org.Google Scholar
- Note, J.-B. and Rannaud, E. 2008. From the bitstream to the netlist. In Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays (FPGA’08). ACM, 264--264. Google Scholar
Digital Library
- Poetter, A., Hunter, J., Patterson, C., and Athanas, P. 2004a. JHDLBits. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA’04).Google Scholar
- Poetter, A., Hunter, J., Patterson, C., Athanas, P., Nelson, B., and Steiner, N. 2004b. JHDLBits: The merging of two worlds. In Proceedings of the 14th International Workshop on Field-Programmable Logic and Applications (FPL’04).Google Scholar
- Raaijmakers, S. and Wong, S. 2007. Run-Time partial reconfiguration for removal, placement and routing on the virtex-II pro. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL’07).Google Scholar
- Raghavan, A. K. and Sutton, P. 2002. JPG - A partial bitstream generation tool to support partial reconfiguration in virtex FPGAs. In Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS’02). IEEE Computer Society, 192. Google Scholar
Digital Library
- Sidhu, R. P. S. and Prasanna, V. K. 2002. Efficient metacomputation using self-reconfiguration. In Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications (FPL’02). Springer, 698--709. Google Scholar
Digital Library
- Steiner, N. J. 2002. A standalone wire database for routing and tracing in xilinx virtex, virtex-E, and virtex-II FPGAs. M.S. thesis, Virginia Polytechnic Institute and State University, Blacksburg, VA.Google Scholar
- Sun. 1999. The java hotspot performance engine architecture. Tech. rep.Google Scholar
- Welsh, D. J. A. and Powell, M. B. 1967. An upper bound for the chromatic number of a graph and its application to timetabling problems. Comput. J. 10, 1, 85--86.Google Scholar
- Wirthlin, M. J. and Hutchings, B. L. 1997. Improving functional density through run-time constant propagation. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays. 86--92. Google Scholar
Digital Library
- Xilinx. 2007a. Virtex-II Pro and Virtex-II Pro X FPGA user guide, UG012 (v4.2). Tech. rep., Xilinx.Google Scholar
- Xilinx. 2007b. Virtex-II Pro and Virtex-II Pro X platform FPGAs: complete data sheet, DS083 (v4.6). Tech. rep., Xilinx.Google Scholar
Index Terms
Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation
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