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A Scalable and Programmable Modular Traffic Manager Architecture

Published:01 May 2011Publication History
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Abstract

A key issue in the design of next-generation Internet routers and switches will be provision of Traffic Manager (TM) functionality in the datapaths of their high-speed switching fabrics. A new architecture that allows dynamic deployment of different TM functions is presented. By considering the processing requirements of operations such as policing and congestion, queuing, shaping, and scheduling, a solution has been derived that is scalable with a consistent programmable interface. Programmability is achieved using a function computation unit which determines the action (e.g., drop, queue, remark, forward) based on the packet attribute information and a memory storage part. Results of a Xilinx Virtex-5 FPGA reference design are presented.

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            cover image ACM Transactions on Reconfigurable Technology and Systems
            ACM Transactions on Reconfigurable Technology and Systems  Volume 4, Issue 2
            May 2011
            216 pages
            ISSN:1936-7406
            EISSN:1936-7414
            DOI:10.1145/1968502
            Issue’s Table of Contents

            Copyright © 2011 ACM

            Publisher

            Association for Computing Machinery

            New York, NY, United States

            Publication History

            • Published: 1 May 2011
            • Accepted: 1 December 2009
            • Revised: 1 October 2009
            • Received: 1 December 2008
            Published in trets Volume 4, Issue 2

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