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Fast Optical Reconfiguration of a Nine-Context DORGA Using a Speed Adjustment Control

Published:01 May 2011Publication History
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Abstract

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits. Such dynamic reconfiguration requires two important features: fast reconfiguration and numerous reconfiguration contexts. However, fast reconfiguration and numerous reconfiguration contexts share a trade-off relation on current VLSIs. Therefore, Optically Reconfigurable Gate Arrays (ORGAs) have been developed to resolve this dilemma. An ORGA architecture allows many configuration contexts by exploiting the large storage capacity of a holographic memory and fast reconfiguration using wide-bandwidth optical connections between a holographic memory and a programmable gate array VLSI. In addition, Dynamic Optically Reconfigurable Gate Arrays (DORGAs) using a photodiode memory architecture have already been developed to realize a high-gate-density VLSI. Therefore, this article presents the first demonstration of a nanosecond-order configuration of a nine-context DORGA architecture. Moreover, this article presents a proposal of a reconfiguration period adjustment technique to control each reconfiguration period to its best setting.

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  1. Fast Optical Reconfiguration of a Nine-Context DORGA Using a Speed Adjustment Control

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    Reviews

    Norian Marranghello

    Since 2004, Watanabe, one of the authors, has been researching optically reconfigurable gate array (ORGA) architectures. This paper goes one step further, including dynamic configuration from multiple previously chosen contexts. A dynamic ORGA (DORGA) architecture includes a very-large-scale integration (VLSI) field-programmable gate array (FPGA)-like island-style gate array. To achieve high gate count, the gate array is programmed through photodiodes arranged in a scheme similar to dynamic random access memory (DRAM). To (re)set the configuration of the gate array, the authors use a holographic memory and a laser system. The authors report that, besides resulting in a much higher gate density (reaching tens of thousands of gates) with respect to the previous versions (at most a few thousand gates), DORGA memory architecture presents an interesting reconfiguration (on the order of hundreds of nanoseconds) to retention (on the order of tens of microseconds) time ratio. However, such times are dependent on the context pattern used, and must be known in advance since they are used for managing the required refresh time periods. Although this paper presents a very interesting approach to dynamic hardware reconfiguration, the main drawback is that the authors do not say anything about how the optical subsystem would be miniaturized to render the whole system commercially practical. Online Computing Reviews Service

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