Abstract
As reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchronization in a way that is scalable and easy to program becomes a challenge. Transactional Memory (TM) is a potential solution to this problem, and an FPGA-based system provides the opportunity to support TM in hardware (HTM). Although there are many proposed approaches to HTM support for ASICs, these do not necessarily map well to FPGAs. In particular in this work we demonstrate that while signature-based conflict detection schemes (essentially bit-vectors) should intuitively be a good match to the bit parallelism of FPGAs, previous approaches result in unacceptable multicycle stalls, operating frequencies, or false-conflict rates. Capitalizing on the reconfigurable nature of FPGA-based systems, we propose an application-specific signature mechanism for HTM conflict detection. Our evaluation uses real and projected FPGA-based soft multiprocessor systems that support HTM and implement threaded, shared-memory network packet processing applications. We find that our application-specific approach: (i) maintains a reasonable operating frequency of 125 MHz, (ii) achieves a 9% to 71% increase in packet throughput relative to signatures with bit selection on a 2-thread architecture, and (iii) allows our HTM to achieve 6%, 54%, and 57% increases in packet throughput on an 8-thread architecture versus a baseline lock-based synchronization for three of four packet processing applications studied, due to reduced false synchronization.
- Bloom, B. H. 1970. Space/Time trade-offs in hash coding with allowable errors. Comm. ACM 13, 7, 422--426. Google Scholar
Digital Library
- Carter, J. L. and Wegman, M. N. 1979. Universal classes of hash functions. J. Comput. Syst. Sci. 18, 2, 143--154.Google Scholar
Digital Library
- Ceze, L., Tuck, J., Torrellas, J., and Cascaval, C. 2006. Bulk disambiguation of speculative threads in multiprocessors. In Proceedings of the Annual International Symposium on Computer Architecture (ISCA'06). 227--238. Google Scholar
Digital Library
- Grinberg, S. and Weiss, S. 2006. Investigation of transactional memory using FPGAs. In Proceedings of the IEEE Convention of Electrical and Electronics Engineers in Israel (EEEI'06). 119--122.Google Scholar
- Kachris, C. and Kulkarni, C. 2007. Configurable transactional memory. In Proceedings of the Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'07). IEEE Computer Society, 65--72. Google Scholar
Digital Library
- Khuller, S., Moss, A., and Naor, J. S. 1999. The budgeted maximum coverage problem. Inf. Process. Lett. 70, 1, 39--45. Google Scholar
Digital Library
- Labrecque, M., Jeffrey, M., and Steffan, J. G. 2010. Application-Specific signatures for transactional memory in soft processors. In Proceedings of the International Workshop on Applied Reconfigurable Compuring (ARC'10). Google Scholar
Digital Library
- Labrecque, M. and Steffan, J. G. 2009. Fast critical sections via thread scheduling for FPGA-based multithreaded processors. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'09).Google Scholar
- Labrecque, M. and Steffan, J. G. 2010. The case for hardware transactional memory in software packet processing. In Proceedings of the ACM/IEEE Symposium on Architecture for Networking and Communications Systems (ANCS'10). Google Scholar
Digital Library
- Labrecque, M., Yiannacouras, P., and Steffan, J. G. 2008. Scaling soft processor systems. In Proceedings of the Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'08). Google Scholar
Digital Library
- Lockwood, J. W., McKeown, N., Watson, G., Gibb, G., Hartke, P., Naous, J., Raghuraman, R., and Luo, J. 2007. NetFPGA—An open platform for gigabit-rate network switching and routing. In Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE'07). Google Scholar
Digital Library
- Minh, C. C., Chung, J., Kozyrakis, C., and Olukotun, K. 2008. STAMP: Stanford transactional applications for multi-processing. In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC'08).Google Scholar
- Otoo, E. J. and Effah, S. 1995. Red-Black trie hashing. Tech. rep. TR-95-03, Carleton.Google Scholar
- Quislant, R., Gutierrez, E., and Plata, O. 2009. Improving signatures by locality exploitation for transactional memory. In Proceedings of the International Conference on Parallel Computing Technologies (PaCT'09). 303--312. Google Scholar
Digital Library
- Sanchez, D., Yen, L., Hill, M. D., and Sankaralingam, K. 2007. Implementing signatures for transactional memory. In Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture (MICRO'07). 123--133. Google Scholar
Digital Library
- Teodorescu, R. and Torrellas, J. 2005. Prototyping architectural support for program rollback using FPGAs. In Proceedings of the Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05). 23--32. Google Scholar
Digital Library
- Wee, S., Casper, J., Njoroge, N., Tesylar, Y., Ge, D., Kozyrakis, C., and Olukotun, K. 2007. A practical FPGA-based framework for novel CMP research. In Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA'07). Google Scholar
Digital Library
- Yen, L., Bobba, J., Marty, M. R., Moore, K. E., Volos, H., Hill, M. D., Swift, M. M., and Wood, D. A. 2007. LogTM-SE: Decoupling hardware transactional memory from caches. In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA'07). 261--272. Google Scholar
Digital Library
- Yen, L., Draper, S., and Hill, M. 2008. Notary: Hardware techniques to enhance signatures. In Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture (MICRO'08). 234--245. Google Scholar
Digital Library
Index Terms
Application-specific signatures for transactional memory in soft processors
Recommendations
Application-specific signatures for transactional memory in soft processors
ARC'10: Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and ApplicationsAs reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchronization in a way that is scalable and easy to program becomes a challenge. ...
NetTM: faster and easier synchronization for soft multicores via transactional memory
FPGA '11: Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arraysWe propose NetTM: support for hardware transactional memory (HTM) in an FPGA-based soft multithreaded multicore that matches the strengths of FPGAs. We evaluate our system using the NetFPGA [6] platform and four network packet processing applications ...
Unbounded page-based transactional memory
Proceedings of the 2006 ASPLOS ConferenceExploiting thread level parallelism is paramount in the multicore era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded programming model. Virtualized transactions (unbounded in space and time) are ...






Comments