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Leveraging reconfigurability in the hardware/software codesign process

Published:22 August 2011Publication History
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Abstract

Current technology allows designers to implement complete embedded computing systems on a single FPGA. Using an FPGA as the implementation platform introduces greater flexibility into the design process and allows a new approach to embedded system design. Since there is no cost to reprogramming an FPGA, system performance can be measured on-chip in the runtime environment and the system's architecture can be altered based on an evaluation of the data to meet design requirements.

In this article, we discuss a new hardware/software codesign methodology tailored to reconfigurable platforms and a design infrastructure created to incorporate on-chip design tools. This methodology utilizes the FPGA's reconfigurability during the design process to profile and verify system performance, thereby reducing system design time. Our current design infrastructure includes: a system specification tool, two on-chip profiling tools, and an on-chip system verification tool.

References

  1. Altera. 2011a. Quartus II. http://www.altera.com/products/software/pld/products/q2/qts-index.html.Google ScholarGoogle Scholar
  2. Altera. 2011b. SOPC builder. http://www.altera.com/products/software/system/products/sopc/sop-index.html.Google ScholarGoogle Scholar
  3. Balarin, F., Chiodo, M., Giusto, P., Hsieh, H., Jurecska, A., Lavagno, L., Passerone, C., Sangiovanni-Vincentelli, A., Sentovich, E., Suzuki, K., and Tabbara, B. 1997. Hardware-Software Co-Design of Embedded Systems: The Polis Approach. Kluwer Academic Press, Dordrecht. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Baleani, M., Gennari, F., Jiang, Y., Patel, Y., Brayton, R. K., and Sangiovanni-Vincentelli, A. 2002. HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform. In Proceedings of the 10th International Symposium on Hardware/Software Codesign. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Browne, S., J.Dongarra, Garner, N., Ho, G., and Mucci, P. 2000. A portable programming interface for performance evaluation on modern processors. Int. J. High Perform. Comput. Appl. 14, 3. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Cai, L. and Gajski, D. 2003. Transaction level modeling: An overview. In Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. 19--24. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Caldari, M., Conti, M., Coppola, M., Curaba, S., Pieralisi, L., and Turchetti, C. 2003. Transaction-Level models for AMBA bus architecture using systemC 2.0. In Proceedings of the Design, Automation and Test in Europe Conference. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Densmore, D., Donlin, A., and Sangiovanni-Vincentelli, A. 2006. FPGA architecture characterization for system level performance analysis. In Proceedings of the Design, Automation and Test in Europe Conference. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Ernst, R., Henkel, J., and Benner, T. 1993. Hardware-Software cosynthesis for microcontrollers. IEEE Desi. Test Comput. 10, 4, 64--75. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Filion, L., Cantin, M.-A., Moss, L., Aboulhamid, E. M., and Bois, G. 2007. Space codesign: A systemC framework for fast exploration of hardware/software systems. In Proceedings of the Design and Verification Conference and Exhibition.Google ScholarGoogle Scholar
  11. Finc, M. and Zemva, A. 2005. Profiling soft-core processor applications for hardware/software partitioning. J. Syst. Archit. 51, 5, 315--329. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. First Silicon Solutions. 2009. Home page http://www.fs2.com.Google ScholarGoogle Scholar
  13. Fleischmann, J., Buchenrieder, K., and Kress, R. 1999. Codesign of embedded systems based on Java and reconfigurable hardware components. In Proceedings of the Conference and Exhibition on Design, Automation and Test in Europe (DATE). Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. GDB. 2009. Home page http://sourceware.org/gdb/.Google ScholarGoogle Scholar
  15. GNU. 2011a. gprof manual. http://www.gnu.org/manual/gprof-2.9.1/gprof.html.Google ScholarGoogle Scholar
  16. GNU. 2011b. The GNU project and free software foundation (FSF). http://www.gnu.org.Google ScholarGoogle Scholar
  17. Hebert, O., K., I. C., and Savaria, Y. 2000. A method to derive application-specific embedded processing cores. In Proceedings of the 8th International Symposium on Hardware/Software Codesign. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Hemmert, K. S., Tripp, J. L., Hutchings, B., and Jackson, P. A. 2003. Source level debugger for the sea cucumber synthesizing compiler. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). 228--237. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Hough, R., Jones, P., Friedman, S., Chamberlain, R., Fritts, J., Lockwood, J., and Cytron, R. 2006. Cycle-Accurate microarchitecture performance evaluation. In Proceedings of the Workshop on Introspective Architecture.Google ScholarGoogle Scholar
  20. Kahn, G. 1974. The semantics of a simple language for parallel programming. In Proceedings of the IPIF Congress.Google ScholarGoogle Scholar
  21. Kimura, S., Itou, Y., and Hirao, M. 1997. A hardware/software codesign method for a general purpose reconfigurable co-processor. In Proceedings of the 5th International Workshop on Hardware/Software Co-Design. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Korn, W., Teller, P., and Castillo, G. 2001. Just how accurate are performance counters? In Proceedings of the 20th IEEE International Performance, Computing, and Communications Conference.Google ScholarGoogle Scholar
  23. Lee, E. and Parks, T. 1995. Dataflow process networks. Proc. IEEE 83, 5, 773--799.Google ScholarGoogle Scholar
  24. Li, Y., Callahan, T., Darnell, E., Harr, R., Kurkure, U., and Stockwood, J. 2000. Hardware-Software co-design of embedded reconfigurable architectures. In Proceedings of the 37th IEEE/ACM Design Automation Conference (DAC). Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. Lysaght, P., Blodget, B., Mason, J., Young, J., and Bridgford, B. 2006. Invited paper: Enhanced architectures, design methodologies, and CAD tools for dynamic reconfiguration of Xilinx FPGAs. In Proceedings of the IEEE International Conference on Field-Programmable Logic and Applications (FPL). 12--17.Google ScholarGoogle Scholar
  26. Magarshack, P. and Paulin, P. G. 2003. System-on-Chip beyond the nanometer wall. In Proceedings of the 40th IEEE/ACM Design Automation Conference (DAC). 419--424. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. MEDEA+. 2003. MEDEA+ EDA roadmap 2003: Executive summary europe. http://www.medea.org/webpublic/publications/publ_relation_eda.htm.Google ScholarGoogle Scholar
  28. Mentor Graphics. 2009. Mentor graphics' seamless co-verification simulator. http://www.mentor.com/seamless.Google ScholarGoogle Scholar
  29. Model Technology. 2009. Home page http://www.model.com.Google ScholarGoogle Scholar
  30. Noguera, J. and Badia, R. M. 2002. Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures. In Proceedings of the 10th International Symposium on Hardware/Software Codesign. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. Ohba, N. and Takano, K. 2004. An SoC design methodology using FPGAs and embedded microprocessors. In Proceedings of the ACM/IEEE Design Automation Conference (DAC). 747--752. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. PAPI. 2009. Home page http://icl.cs.utk.edu/projects/papi/.Google ScholarGoogle Scholar
  33. Rakhmatov, D. N. and Vrudhula, S. B. K. 2002. Hardware/Software bipartitioning for dynamically reconfigurable systems. In Proceedings of the 10th International Symposium on Hardware/Software Codesign. Google ScholarGoogle ScholarDigital LibraryDigital Library
  34. Rissa, T., Luk, W., and Cheung, P. 2004. Automated combination of simulation and hardware prototyping. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms.Google ScholarGoogle Scholar
  35. Saldana, M., Shannon, L., and Chow, P. 2006. The routability of multiprocessor network topologies in FPGAs. In Proceedings of the IEEE/ACM SLIP Workshop. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. Shannon, L. and Chow, P. 2004a. Maximizing system performance: Using reconfigurability to monitor system communications. In Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT). 231--238.Google ScholarGoogle Scholar
  37. Shannon, L. and Chow, P. 2004b. Using reconfigurability to achieve real-time profiling for hardware/software codesign. In Proceedings of the ACM International Symposium on FPGAs. 190--199. Google ScholarGoogle ScholarDigital LibraryDigital Library
  38. Shannon, L. and Chow, P. 2007. SIMPPL: An adaptable soc framework using a progammable IP interface to facilitate design reuse. IEEE Trans. VLSI Syst. 15, 377--390. Google ScholarGoogle ScholarDigital LibraryDigital Library
  39. Shannon, L., Fort, B., Parikh, S., Patel, A., Saldana, M., and Chow, P. 2006. A system design methodology for reducing system integration time and facilitating modular design verification. In Proceedings of the IEEE International Conference on Field-Programmable Logic and Applications (FPL).Google ScholarGoogle Scholar
  40. Sprunt, B. 2002. Pentium 4 performance-monitoring features. IEEE Micro 22, 4. Google ScholarGoogle ScholarDigital LibraryDigital Library
  41. Stitt, G., Lysecky, R., and Vahid, F. 2003. Dynamic hardware/software partitioning: A first approach. In Proceedings of the 40th IEEE/ACM Design Automation Conference (DAC). 250--255. Google ScholarGoogle ScholarDigital LibraryDigital Library
  42. Weicker, R. P. 1984. Dhrystone: A synthetic systems programming benchmark. Comm. ACM 27, 10. Google ScholarGoogle ScholarDigital LibraryDigital Library
  43. Xilinx. 2011a. ChipScope pro's home page. http://www.xilinx.com/ise/optional_prod/cspro.htm.Google ScholarGoogle Scholar
  44. Xilinx. 2011b. EDK design tools. http://www.xilinx.com/ise/embedded_design_prod/platform_studio.htm.Google ScholarGoogle Scholar
  45. Xilinx. 2011c. MicroBlaze debug module (MDM) documentation. http://www.xilinx.com/support/documentation/ip_documentation/mdm.pdf.Google ScholarGoogle Scholar

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      • Published in

        cover image ACM Transactions on Reconfigurable Technology and Systems
        ACM Transactions on Reconfigurable Technology and Systems  Volume 4, Issue 3
        August 2011
        204 pages
        ISSN:1936-7406
        EISSN:1936-7414
        DOI:10.1145/2000832
        Issue’s Table of Contents

        Copyright © 2011 ACM

        Publisher

        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 22 August 2011
        • Accepted: 1 December 2010
        • Revised: 1 August 2010
        • Received: 1 August 2008
        Published in trets Volume 4, Issue 3

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