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Static bus schedule aware scratchpad allocation in multiprocessors

Published:11 April 2011Publication History
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Abstract

Compiler controlled memories or scratchpad memories offer more predictable program execution times than cache memories. Scratchpad memories are often employed in multi-processor system-on-chip (MPSoC) platforms which seek to meet the performance needs of embedded applications while limiting power consumption and timing unpredictability. Scratchpad allocation schemes optimize performance while ensuring predictable execution times (as compared to caches).

In this work, we develop a compile-time scratchpad allocation framework for multi-processor platforms, where the processors (virtually) share on-chip scratchpad space and external memory is accessed through a shared bus. Our allocation method considers the waiting time for bus access while deciding which memory blocks to load into the shared scratchpad memory space. Incorporating the bus schedule into our scratchpad allocation method leads to a global optimization of an application, as compared to employing local scratchpad allocation schemes in individual processors which locally optimize the per-processor execution time. We evaluate the efficacy, sensitivity and efficiency of our memory allocation scheme on two real-world embedded applications - an application controlling an Unmanned Aerial Vehicle (UAV), and a (fragment of) an in-orbit spacecraft software.

References

  1. M.T. Kandemir, J. Ramanujam, and A.N. Choudhary. Exploiting shared scratch pad memory space in embedded multiprocessor systems. In DAC, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. J.-F. Deverge and I. Puaut. WCET-directed dynamic scratchpad memory allocation of data. In ECRTS, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. P. R. Panda, N. D. Dutt, and A. Nicolau. On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. ACM Trans. Des. Autom. Electron. Syst., 5(3), 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. M. Verma, L. Wehmeyer, and P. Marwedel. Cache-aware scratchpad allocation algorithm. In DATE, 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. S. Steinke, L. Wehmeyer, B. Lee, and P. Marwedel. Assigning program and data objects to scratchpad for energy reduction. In DATE, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. S. Udayakumaran and R. Barua. Compiler-decided dynamic memory allocation for scratch-pad based embedded systems. In CASES, 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. M. Verma, L. Wehmeyer, and P. Marwedel. Dynamic overlay of scratchpad memory for energy minimization. In CODES Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. ISSS, 2004.Google ScholarGoogle Scholar
  9. V. Suhendra, T. Mitra, A. Roychoudhury, and T. Chen. WCET centric data allocation to scratchpad memory. In RTSS, 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. I. Puaut. WCET-centric software-controlled instruction caches for hard real-time systems. In ECRTS, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. H. Falk and J.C. Kleinsorge. Optimal static WCET-aware scratchpad allocation of program code. In DAC, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. M. Verma, K. Petzold, L. Wehmeyer, H. Falk, and P. Marwedel. Scratchpad sharing strategies for multiprocess embedded systems: A first approach. In ESTImedia, 2005.Google ScholarGoogle ScholarCross RefCross Ref
  13. V. Suhendra, C. Raghavan, and T. Mitra. Integrated scratchpad memory optimization and task scheduling for MPSoC architectures. In CASES, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. M. Kandemir, O. Ozturk, and M. Karakoy. Dynamic on-chip memory management for chip multiprocessors. In CASES, 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. V. Suhendra, A. Roychoudhury, and T. Mitra. Scratchpad allocation for concurrent embedded software. ACM Trans. Program. Lang. Syst., 32(4), 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. S. Chattopadhyay, A. Roychoudhury, and T. Mitra. Modeling shared cache and bus in multi-cores for timing analysis. In SCOPES, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. D. J. A. Welsh and M. B. Powell. An upper bound for the chromatic number of a graph and its application to timetabling problems. The Computer Journal, 10(1), 1967.Google ScholarGoogle ScholarCross RefCross Ref
  18. European Space Agency. DEBIE -- First standard space debris monitoring instrument, 2008. Available at: http://gate.etamax.de/edid/publicaccess/debie1.php.Google ScholarGoogle Scholar
  19. F. Nemer, H. Cassé, P. Sainrat, J.P. Bahsoun, and M. De Michiel. Papabench: a free real-time benchmark. In WCET Workshop, 2006.Google ScholarGoogle Scholar
  20. M. Gschwind. The Cell broadband engine: exploiting multiple levels of parallelism in a chip multiprocessor. Int. J. Parallel Program., 35(3), 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library

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      • Published in

        cover image ACM SIGPLAN Notices
        ACM SIGPLAN Notices  Volume 46, Issue 5
        LCTES '10
        May 2011
        170 pages
        ISSN:0362-1340
        EISSN:1558-1160
        DOI:10.1145/2016603
        Issue’s Table of Contents
        • cover image ACM Conferences
          LCTES '11: Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
          April 2011
          182 pages
          ISBN:9781450305556
          DOI:10.1145/1967677

        Copyright © 2011 ACM

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        Association for Computing Machinery

        New York, NY, United States

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        • Published: 11 April 2011

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