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Cache persistence analysis: a novel approachtheory and practice

Published:11 April 2011Publication History
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Abstract

To compute a worst-case execution time (WCET) estimate for a program, the architectural effects of the underlying hardware must be modeled. For modern processors this results in the need for a cache and pipeline analysis. The timing-relevant result of the cache analysis is the categorization of the accesses to cached memory. Categorizations that are obtainable by the well-known must and may cache analysis are always-hit, always-miss and not-classified. The cache persistence analysis tries to provide additional information for the not-classified case to limit the number of misses.

There exists a cache persistence analysis by Ferdinand and Wilhelm based on abstract interpretation computing these classifications. In this paper, we present a correctness issue with this analysis and a novel analysis that fixes it. For fully timing compositional architectures the persistence information is straightforward to use. We will focus on the application of the persistence analysis for state-of-the-art architectures that show timing anomalies. Such architectures do not allow to quantify the costs of a single cache hit or miss in isolation. To make the usage of the persistence information feasible, we integrate the novel persistence analysis together with a novel path analysis approach into the industrially used WCET analyzer aiT.

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    • Published in

      cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 46, Issue 5
      LCTES '10
      May 2011
      170 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/2016603
      Issue’s Table of Contents
      • cover image ACM Conferences
        LCTES '11: Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
        April 2011
        182 pages
        ISBN:9781450305556
        DOI:10.1145/1967677

      Copyright © 2011 ACM

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      • Published: 11 April 2011

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