Abstract
To compute a worst-case execution time (WCET) estimate for a program, the architectural effects of the underlying hardware must be modeled. For modern processors this results in the need for a cache and pipeline analysis. The timing-relevant result of the cache analysis is the categorization of the accesses to cached memory. Categorizations that are obtainable by the well-known must and may cache analysis are always-hit, always-miss and not-classified. The cache persistence analysis tries to provide additional information for the not-classified case to limit the number of misses.
There exists a cache persistence analysis by Ferdinand and Wilhelm based on abstract interpretation computing these classifications. In this paper, we present a correctness issue with this analysis and a novel analysis that fixes it. For fully timing compositional architectures the persistence information is straightforward to use. We will focus on the application of the persistence analysis for state-of-the-art architectures that show timing anomalies. Such architectures do not allow to quantify the costs of a single cache hit or miss in isolation. To make the usage of the persistence information feasible, we integrate the novel persistence analysis together with a novel path analysis approach into the industrially used WCET analyzer aiT.
- C. Ballabriga and H. Cassé. Improving the first-miss computation in set-associative instruction caches. In ECRTS, pages 341--350, 2008. Google Scholar
Digital Library
- H. Cassé and P. Sainrat. OTAWA, a framework for experimenting WCET computations. In Proceedings of the 3rd European Congress on Embedded Real-Time Software, pages 25--27, 2005.Google Scholar
- P. Cousot and R. Cousot. Abstract interpretation: A unified lattice model for static analysis of programs by construction or approximation of fixpoints. In POPL, pages 238--252, 1977. Google Scholar
Digital Library
- A. Ermedahl. A Modular Tool Architecture for Worst-Case Execution-Time Analysis. PhD thesis, Uppsala University, 2003.Google Scholar
- C. Ferdinand. Cache Behavior Prediction for Real-Time Systems. PhD Thesis, Universität des Saarlandes, 1997.Google Scholar
- C. Ferdinand and R. Wilhelm. Efficient and precise cache behavior prediction for real-time systems. Real-Time Systems, 17 (2--3): 131--181, 1999. Google Scholar
Digital Library
- C. Ferdinand, F. Martin, R. Wilhelm, and M. Alt. Cache behavior prediction by abstract interpretation. In Science of Computer Programming, pages 52--66. Springer, 1996. Google Scholar
Digital Library
- C. Ferdinand, R. Heckmann, M. Langenbach, F. Martin, M. Schmidt, H. Theiling, S. Thesing, and R. Wilhelm. Reliable and precise WCET determination for a real-life processor. In Conference on Embedded Software (EMSOFT), volume 2211 of LNCS, 2001. Google Scholar
Digital Library
- C. Ferdinand, F. Martin, C. Cullmann, M. Schlickling, I. Stein, S. Thesing, and R. Heckmann. New Developments in WCET Analysis. In T. Reps, M. Sagiv, and J. Bauer, editors, Program Analysis and Compilation, Theory and Practice: Essays dedicated to Reinhard Wilhelm, volume 4444 of LNCS, pages 12--52. Springer Verlag, 2007. Google Scholar
Digital Library
- G. Gebhard. Timing anomalies reloaded. In B. Lisper, editor, Proceedings of 10th International Workshop on Worst-Case Execution Time (WCET) Analysis, pages 5--15. Austrian Computer Society, July 2010.Google Scholar
- C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In Real-Time Systems Symposium (RTSS), 1995. Google Scholar
Digital Library
- R. Heckmann, M. Langenbach, S. Thesing, and R. Wilhelm. The influence of processor architecture on the design and the results of WCET tools. Real-Time Systems, 91 (7): 1038--1054, 2003.Google Scholar
Cross Ref
- B. Lesage, D. Hardy, and I. Puaut. WCET analysis of multi-level set-associative data caches. In N. Holsti, editor, 9th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, Dagstuhl, Germany, 2009. Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany. URL http://drops.dagstuhl.de/opus/volltexte/2009/2283.Google Scholar
- R. Lougee-Heimer. The common optimization interface for operations research: Promoting open-source software in the operations research community. IBM J. Res. Dev., 47 (1): 57--66, 2003. ISSN 0018--8646. http://dx.doi.org/10.1147/rd.471.0057. Google Scholar
Digital Library
- T. Lundqvist and P. Stenström. Timing anomalies in dynamically scheduled microprocessors. In Real-Time Systems Symposium (RTSS), December 1999. Google Scholar
Digital Library
- N. Matthies. Präzise Bestimmung längster Programmpfade anhand von Zustandsgraphen unter Berücksichtigung von Schleifen-Nebenbedingungen. Diplomarbeit an der Universität des Saarlandes FB 6.2 (Wilhelm), Universität des Saarlandes, February 2006.Google Scholar
- F. Mueller, D. B. Whalley, and M. Harmon. Predicting instruction cache behavior. In ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, 1994.Google Scholar
- J. Reineke. Caches in WCET Analysis. PhD thesis, Universität des Saarlandes, November 2008.Google Scholar
- J. Reineke, B. Wachter, S. Thesing, R. Wilhelm, I. Polian, J. Eisinger, and B. Becker. A definition and classification of timing anomalies. In Workshop on Worst-Case Execution-Time Analysis (WCET), July 2006.Google Scholar
- A. J. Smith. Cache memories. ACM Computing Surveys, 14 (3): 473--530, 1982. ISSN 0360-0300. http://doi.acm.org/10.1145/356887.356892. Google Scholar
Digital Library
- J. Souyris, E. Le Pavec, G. Himbert, V. Jégu, G. Borios, and R. Heckmann. Computing the worst case execution time of an avionics program by abstract interpretation. In Proceedings of the 5th Intl Workshop on Worst-Case Execution Time (WCET) Analysis, pages 21--24, 2005.Google Scholar
- L. Tan. The worst case execution time tool challenge 2006: Technical report for the external test. In Proc. 2nd International Symposium on Leveraging Applications of Formal Methods (ISOLA'06), 2006. Google Scholar
Digital Library
- H. Theiling. Control Flow Graphs For Real-Time Systems Analysis. PhD thesis, Universität des Saarlandes, 2002.Google Scholar
- H. Theiling, C. Ferdinand, and R. Wilhelm. Fast and precise WCET prediction by separated cache and path analyses. Real-Time Systems, 18 (2/3): 157--179, May 2000. Google Scholar
Digital Library
- S. Thesing. Safe and Precise WCET Determinations by Abstract Interpretation of Pipeline Models. PhD thesis, Universität des Saarlandes, 2004.Google Scholar
- S. Thesing, J. Souyris, R. Heckmann, F. Randimbivololona, M. Langenbach, R. Wilhelm, and C. Ferdinand. An abstract-interpretation-based timing validation of hard real-time avionics software systems. In Dependable Systems and Networks (DSN), June 2003.Google Scholar
- R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, and C. Ferdinand. Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems. IEEE Transactions on CAD of Integrated Circuits and Systems, 28 (7): 966--978, July 2009. 10.1109/TCAD.2009.2013287. Google Scholar
Digital Library
Index Terms
Cache persistence analysis: a novel approachtheory and practice
Recommendations
Cache persistence analysis: Theory and practice
Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systemsTo compute a worst-case execution time (WCET) estimate for a program, the architectural effects of the underlying hardware must be modeled. For modern processors this results in the need for a cache and pipeline analysis.
The timing-relevant result of ...
Cache persistence analysis: a novel approachtheory and practice
LCTES '11: Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systemsTo compute a worst-case execution time (WCET) estimate for a program, the architectural effects of the underlying hardware must be modeled. For modern processors this results in the need for a cache and pipeline analysis. The timing-relevant result of ...
WCET-driven cache-aware code positioning
CASES '11: Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systemsCode positioning is a well-known compiler optimization aiming at the improvement of the instruction cache behavior. A contiguous mapping of code fragments in memory avoids overlapping of cache sets and thus decreases the number of cache conflict misses.
...







Comments