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Deriving an efficient FPGA implementation of a low density parity check forward error corrector

Published:19 September 2011Publication History
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Abstract

Creating correct hardware is hard. Though there is much talk of using formal and semi-formal methods to develop designs and implementations, in practice most implementations are written without the support of any formal or semi-formal methodology. Having such a methodology brings many benefits, including improved likelihood of a correct implementation, lowering the cost of design exploration and lowering the cost of certification. In this paper, we introduce a semi formal methodology for connecting executable specifications written in the functional language Haskell to efficient VHDL implementations. The connection is performed by manual edits, using semi-formal equational reasoning facilitated by the worker/wrapper transformation, and directed using commutable functors. We explain our methodology on a full-scale example, an efficient Low-Density Parity Check forward error correcting code, which has been implemented on a Virtex-5 FPGA.

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    • Published in

      cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 46, Issue 9
      ICFP '11
      September 2011
      456 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/2034574
      Issue’s Table of Contents
      • cover image ACM Conferences
        ICFP '11: Proceedings of the 16th ACM SIGPLAN international conference on Functional programming
        September 2011
        470 pages
        ISBN:9781450308656
        DOI:10.1145/2034773

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      • Published: 19 September 2011

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