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Compact data structure and scalable algorithms for the sparse grid technique

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Published:12 February 2011Publication History
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Abstract

The sparse grid discretization technique enables a compressed representation of higher-dimensional functions. In its original form, it relies heavily on recursion and complex data structures, thus being far from well-suited for GPUs. In this paper, we describe optimizations that enable us to implement compression and decompression, the crucial sparse grid algorithms for our application, on Nvidia GPUs. The main idea consists of a bijective mapping between the set of points in a multi-dimensional sparse grid and a set of consecutive natural numbers. The resulting data structure consumes a minimum amount of memory. For a 10-dimensional sparse grid with approximately 127 million points, it consumes up to 30 times less memory than trees or hash tables which are typically used. Compared to a sequential CPU implementation, the speedups achieved on GPU are up to 17 for compression and up to 70 for decompression, respectively. We show that the optimizations are also applicable to multicore CPUs.

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          • Published in

            cover image ACM SIGPLAN Notices
            ACM SIGPLAN Notices  Volume 46, Issue 8
            PPoPP '11
            August 2011
            300 pages
            ISSN:0362-1340
            EISSN:1558-1160
            DOI:10.1145/2038037
            Issue’s Table of Contents
            • cover image ACM Conferences
              PPoPP '11: Proceedings of the 16th ACM symposium on Principles and practice of parallel programming
              February 2011
              326 pages
              ISBN:9781450301190
              DOI:10.1145/1941553
              • General Chair:
              • Calin Cascaval,
              • Program Chair:
              • Pen-Chung Yew

            Copyright © 2011 ACM

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            New York, NY, United States

            Publication History

            • Published: 12 February 2011

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