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Choose-your-own-adventure routing: Lightweight load-time defect avoidance

Published:28 December 2011Publication History
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Abstract

Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the intended operational characteristics. Without careful mitigation, component yield rates will fall, potentially negating the economic benefits of scaling. The fine-grained reconfigurability inherent in FPGAs is a powerful tool that can allow us to drop the stringent requirement that every device be fabricated perfectly in order for a component to be useful. To exploit inherent FPGA reconfigurability while avoiding full CAD mapping, we propose lightweight techniques compatible with the current single bitstream model that can avoid defective devices, reducing yield loss at high defect rates. In particular, by embedding testing operations and alternative path configurations into the bitstream, each FPGA can avoid defects by making only simple, greedy decisions at bitstream load time. With 20% additional tracks above the minimum routable channel width, routes can tolerate 0.01% switch and wire defect rates, raising yield from essentially 0% to near 100%.

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          • Published in

            cover image ACM Transactions on Reconfigurable Technology and Systems
            ACM Transactions on Reconfigurable Technology and Systems  Volume 4, Issue 4
            December 2011
            179 pages
            ISSN:1936-7406
            EISSN:1936-7414
            DOI:10.1145/2068716
            Issue’s Table of Contents

            Copyright © 2011 ACM

            Publisher

            Association for Computing Machinery

            New York, NY, United States

            Publication History

            • Published: 28 December 2011
            • Accepted: 1 November 2010
            • Revised: 1 September 2009
            • Received: 1 May 2009
            Published in trets Volume 4, Issue 4

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