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Scalable don't-care-based logic optimization and resynthesis

Published:28 December 2011Publication History
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Abstract

We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reasonable runtime on industrial designs. The approach uses don't-cares computed for a window surrounding a node and can take into account external don't-cares (e.g., unreachable states). It uses a SAT solver for all aspects of Boolean manipulation: computing don't-cares for a node in the window, and deriving a new Boolean function of the node after resubstitution. Experimental results on 6-input LUT networks after a high effort synthesis show substantial reductions in area and delay. When applied to 20 large academic benchmarks, the LUT counts and logic levels are reduced by 45.0% and 12.2%, respectively. The longest runtime for synthesis and mapping is about two minutes. When applied to a set of 14 industrial benchmarks ranging up to 83K 6-LUTs, the LUT counts and logic levels are reduced by 11.8% and 16.5%, respectively. The longest runtime is about 30 minutes.

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      • Published in

        cover image ACM Transactions on Reconfigurable Technology and Systems
        ACM Transactions on Reconfigurable Technology and Systems  Volume 4, Issue 4
        December 2011
        179 pages
        ISSN:1936-7406
        EISSN:1936-7414
        DOI:10.1145/2068716
        Issue’s Table of Contents

        Copyright © 2011 ACM

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 28 December 2011
        • Accepted: 1 November 2010
        • Revised: 1 August 2009
        • Received: 1 May 2009
        Published in trets Volume 4, Issue 4

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