Abstract
The state-of-the-art power-aware clustering tool, P-T-VPack, achieves energy reduction by localizing nets with high switching activity at the expense of channel width and area. In this study, we employ predicted individual postplacement net length information during clustering and prioritize longer nets. This approach targets the capacitance factor for energy reduction, and prioritizes longer nets for channel width and area reduction. We first introduce a new clustering strategy, W-T-VPack, which replaces the switching activity in P-T-VPack with a net length factor. We obtain a 9.87% energy reduction over T-VPack (3.78% increase over P-T-VPack), while at the same time completely eliminating P-T-VPack's channel width and area overhead. We then introduce W-P-T-VPack, which combines switching activity and net length factors. W-P-T-VPack achieves 14.26% energy reduction (0.31% increase over P-T-VPack), while further improving channel width by up to 12.87% for different cluster sizes. We investigate the energy performance of routability (channel width)-driven clustering algorithms, and show that W-T-VPack consistently outperforms T-RPack and iRAC by at least 11.23% and 9.07%, respectively. We conclude that net-length-based clustering is an effective method to concurrently target energy and channel width.
- Actel Corp. 2009a. Webpage. http://www.actel.com/products/iglooseries/default.aspx.Google Scholar
- Actel Corp. 2009b. Webpage. http://www.actel.com/products/pa3/.Google Scholar
- Altera Corp. 2009. Webpage. http://www.altera.com/products/devices/cyclone-about/cyc-about.html.Google Scholar
- Altera Corp. 2008. Webpage. http://www.altera.com/products/devices/stratix-fpgas/stratix-iv/stxiv-index.jsp.Google Scholar
- Betz, V. and Rose, J. 1997. VPR: A new packing, placement and routing tool for FPGA research. In Proceedings of the 7th International Workshop on Field-Programmable Logic. 213--222. Google Scholar
Digital Library
- Betz, V. and Rose, J. 1998. Architecture and CAD for the speed and area optimization of FPGAs. Ph.D. dissertation. University of Toronto.Google Scholar
- Bharadwaj, R. P., Konar, R., Bhatia, D., and Balsara, P. 2005. FPGA architecture for standby power management. In Proceedings of the IEEE International Conference on Field-Programmable Technology. 181--188.Google Scholar
- Bozrgzadeh, E., Memik, S. O., Yang, X. J., and Sarrafzadeh, M. 2004. Routability-Driven packing: Metrics and algorithms for cluster-based FPGAs. J. Circ. Syst. Comput. 13, 1, 77--100.Google Scholar
Cross Ref
- Chen, D. and Cong, J. 2004. Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'04). ACM, New York, 70--73. DOI = http://doi.acm.org/10.1145/1013235.1013259. Google Scholar
Digital Library
- Chen, D. T., Vorwerk, K., and Kennings, A. 2007. Improving timing-driven FPGA packing with physical information. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'07). 117--123.Google Scholar
- Chow, C. T., Tsui, L. S. M., Leong, P. H. W., Luk, W., and Wilton, S. J. E. 2005. Dynamic voltage scaling for commercial FPGAs. In Proceedings of the IEEE International Conference on Field-Programmable Technology. 173--180.Google Scholar
- Hassan, H., Anis, M., Daher, A. E., and Elmasry, M. 2005. Activity packing in FPGAs for leakage power reduction. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'05). IEEE Computer Society, Washington, DC, 212--217. DOI = http://dx.doi.org/10.1109/DATE.2005.48. Google Scholar
Digital Library
- Jamieson, P., Luk, W., Wilton, S. J. E., and Constantinides, G. 2009. An energy and power consumption analysis of FPGA routing architectures. In Proceedings of the International Conference on Field-Programmable Technology. 324--327.Google Scholar
- Kahng, A. B. and Reda, S. 2005. Intrinsic shortest path length: A new, accurate a priori wirelength estimator. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. 173-- 180. Google Scholar
Digital Library
- Karypis, G. and Kumar, V. 1999. Multilevel k-way hypergraph partitioning. In Proceedings of the 36th Annual ACM/IEEE Design Automation Conference (DAC'99), M. J. Irwin, Ed. ACM, New York, 343--348. DOI = http://doi.acm.org/10.1145/309847.309954. Google Scholar
Digital Library
- Lamoureux. J. 2003. On the interaction between power-aware computer-aided design algorithms for field-programmable gate arrays. M.A. thesis. University of British Columbia.Google Scholar
- Lamoureux, J. and Wilton, S. J. 2003. On the interaction between power-aware FPGA CAD algorithms. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. DOI = http://dx.doi.org/10.1109/ICCAD.2003.106. Google Scholar
Digital Library
- Lamoureux, J. and Wilton, S. 2006a. Architecture and CAD for FPGA clock networks. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'06). 1--2.Google Scholar
- Lamoureux, J. and Wilton, S. J. E. 2006b. Activity estimation for field-programmable gate arrays. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'06). 1--8.Google Scholar
- Lamoureux, J. and Wilton, S. J. 2006c. FPGA clock network architecture: Flexibility vs. area and power. In Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays (FPGA'06). ACM, New York, 101--108. DOI = http://doi.acm.org/10.1145/1117201.1117216. Google Scholar
Digital Library
- Lamoureux, J. and Wilton, S. J. 2008. On the trade-off between power and flexibility of FPGA clock networks. ACM Trans. Reconfig. Technol. Syst. 1, 3, 1--33. DOI = http://doi.acm.org/10.1145/1391732.1391733. Google Scholar
Digital Library
- Lamoureux, J., Lemieux, G. G., and Wilton, S. 2008. GlitchLess: Dynamic power minimization in FPGAs through edge alignment and glitch filtering. IEEE Trans. VLSI Syst., 1521--1534. Google Scholar
Digital Library
- Lorenz, M. G., Mengibar, L., Valderas, M. G., and Entrena, L. 2004. Power consumption reduction through dynamic reconfiguration. In Proceedings of the 14th International Conference on Field-Programmable Logic and Applications (FPL'04).Google Scholar
- Marquardt, A., Betz, V., and Rose, J. 1999. Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density. In Proceedings of the ACM/SIGDA 7th International Symposium on Field Programmable Gate Arrays (FPGA'99). ACM, New York, 37--46. DOI = http://doi.acm.org/10.1145/296399.296426. Google Scholar
Digital Library
- Marrakchi, Z., Mrabet, H., and Mehrez, H. 2005. Hierarchical FPGA clustering based on a multilevel partitioning approach to improve routability and reduce power dissapation. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (Reconfig'05). DOI = http://dx.doi.org/10.1109/RECONFIG.2005.23. Google Scholar
Digital Library
- Mondal, S. and Ogrenci Memik, S. 2005. A low power FPGA routing architecture. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS).Google Scholar
- Pandit, A. and Akoglu, A. 2007a. Wirelength prediction for FPGAs. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL'07). 749--752.Google Scholar
- Pandit, A. and Akoglu, A. 2007b. Net length based routability driven packing. In Proceedings of the IEEE International Conference on Field-Programmable Technology (ICFPT'07). 225--232.Google Scholar
- Poon, K., Yan, A., and Wilton, S. 2002. A flexible power model for FPGAs. In Proceedings of the International Conference on Field-Programmable Logic and Applications (FPL'02). 312--321. Google Scholar
Digital Library
- Poon, K. K., Wilton, S. J., and Yan, A. 2005. A detailed power model for field-programmable gate arrays. ACM Trans. Des. Autom. Electron. Syst. 10, 2, 279--302. DOI = http://doi.acm.org/10.1145/1059876.1059881. Google Scholar
Digital Library
- Rahman, A., Das, S., Tuan, T., and Rahut, A. 2005. Heterogeneous routing architecture for low-power FPGA fabric. In Proceedings of the IEEE Custom Integrated Circuits Conference. 183--186.Google Scholar
- Singh, A. and Marek-Sadowska, M. 2002. Efficient circuit clustering for area and power reduction in FPGAs. In Proceedings of the ACM/SIGDA 10th International Symposium on Field-Programmable Gate Arrays (FPGA'02). ACM, New York, 59--66. DOI = http://doi.acm.org/10.1145/503048.503058. Google Scholar
Digital Library
- Tom, M., Leong, D., and Lemieux, G. 2006. Un/DoPack: Re-Clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'06). ACM, New York, 680--687. DOI = http://doi.acm.org/10.1145/1233501.1233643 Google Scholar
Digital Library
- Tom, M. and Lemieux, G. 2005. Logic block clustering of large designs for channel-width constrained FPGAs. In Proceedings of the 42nd Annual Design Automation Conference (DAC'05). ACM, New York, 726--731. DOI = http://doi.acm.org/10.1145/1065579.1065770. Google Scholar
Digital Library
- Xilinx Corp. 2010a. Webpage. http://www.xilinx.com/products/spartan6/index.htm.Google Scholar
- Xilinx Corp. 2010b. Webpage. http://www.xilinx.com/products/virtex6/.Google Scholar
- Xilinx Corp. 2010c. Webpage.http://www.xilinx.com/support/documentation/white_papers/wp373_V7_K7_A7_Devices.pdf.Google Scholar
Index Terms
Net-length-based routability-driven power-aware clustering
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