skip to main content
research-article

Test compression for dynamically reconfigurable processors

Published:28 December 2011Publication History
Skip Abstract Section

Abstract

We present the world's first test compression technique that features automation of compression rules for test time reduction on dynamically reconfigurable processors. Evaluations on an actual 40-nm product show that our technique achieves a 2.7 times compression ratio for original configuration information (better than does GZIP), the peak decompression bandwidth of 1.6 GB/s, and 2.7 times shorter test times.

References

  1. AHA. 2009. 2.5Gbits/sec gzip compression/decompression IC. Product Brief.Google ScholarGoogle Scholar
  2. Alameldeen, A. R. and Wood, D. A. 2004. Frequent pattern compression: A significance-based compression scheme for L2 caches. Tech. rep. 1500, Computer Science Department, UW-Madison.Google ScholarGoogle Scholar
  3. Dandalis, A. and Prasanna, V. K. 2005. Configuration compression for FPGA-based embedded systems. IEEE Trans. VLSI Syst., 13, 12, 1394--1398. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Deutsch, P. 1996. DEFLATE compressed data format specification. RFC 1561, version 1.3.Google ScholarGoogle Scholar
  5. Gu, H. and Chen, S. 2008. Partial reconfiguration bitstream compression for virtex FPGAs. In Proceedings of the Congress on Image and Signal Processing. 183--185. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Hauck, S., Li, Z., and Schwabe, E. 1998. Configuration compression for the Xilinx XC6200 FPGA. In Proceedings of the Symposium on Field-Programmable Custom Computing Machines. 138--146. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Kejelso, M., Gooch, M., and Jones, S. 1996. Design and performance of a main memory hardware data compressor. In Proceedings of the EUROMICRO Conference. 423--430.Google ScholarGoogle Scholar
  8. Khu, A. 2001. Xilinx FPGA configuration data compression and decompression. Whiter Paper, WP152, Xilinx, Inc.Google ScholarGoogle Scholar
  9. Kitaoka, T., Amano, H., and Anjo, K. 2003. Reducing the configuration loading time of a coarse grain multicontext reconfigurable device. In Proceedings of the IEEE International Conference on Field Programmable Logic and Applications. 171--180.Google ScholarGoogle Scholar
  10. Koch, D., Beckhoff, C., and Teich, J. 2009. Hardware decompression techniques for FPGA-based embedded systems. ACM Trans. Reconfig. Technol. Syst. 2, 2, Article 9. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Kodama, T., Tsunoda, T., Takada, M., Tanaka, H., Akita, Y., Sato, M., and Ito, M. 2006. Flexible engine: A dynamic reconfigurable accelerator with high performance and low power consumption. In Proceedings of the IEEE International Symposium on Low-Power and High-Speed Chips (CoolChips). 393--408.Google ScholarGoogle Scholar
  12. Li, Z. and Hauck, S. 2001. Configuration compression for virtex FPGAs. In Proceedings of the Symposium on Field-Programmable Custom Computing Machines. 147--159. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Martina, M., Masera, G., Molino, A., Vacca, F., Sterpone, L., and Violante, M. 2006. A new approach to compress the configuration information of programmable devices. In Proceedings of the Conference on Design, Automation and Test in Europe. 48--51. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Mei, B., Lambrechts, A., Verkest, D., Mignolet, J.-Y., and Lauwereins, R. 2005. Architecture exploration for a reconfigurable architecture template. IEEE Des. Test Comput. 22, 2, 90--101. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Motomura, M. 2008. C-Based programmable hardware core “STP Engine”: Current status and the future. IEICE Tech. rep., 108(300), 51--56.Google ScholarGoogle Scholar
  16. Nunez-Yanez, J. L. and Chouliaras, V. A. 2006. Gigabyte per second streaming lossless data compression hardware based on a configurable variable-geometry CAM dictionary. In IEE Proceedings of the Comput. Digital Techn. 153, 1, 47--58.Google ScholarGoogle ScholarCross RefCross Ref
  17. Pan, J. H., Mitra, T., and Wong, W.-F. 2004. Configuration bitstream compression for dynamically reconfigurable FPGAs. In Proceedings of the International Conference on Computers Aided Design. 766--773. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Saito, S., Kohama, Y., Sugimori, Y., Hasegawa, Y., Matsutani, H., Sano, T., Kasuga, K., Yoshida, Y., Niitsu, K., Miura, N., Kuroda, T., and Amano, H. 2009. Muccra-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. In Proceedings of the IEEE International Conference on Field Programmable Logic and Applications. 6--11.Google ScholarGoogle Scholar
  19. Sayood, K. 1996. Introduction to Data Compression. Morgan Kaufmann Publisher. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Stefan, R. and Cotofana, S. D. 2008. Bitstream compression techniques for virtex 4 FPGAs. In Proceedings of the International Conference on Field Programmable Logic and Applications. 323--328.Google ScholarGoogle Scholar
  21. Tahoori, M. B. and Mitra, S. 2006. Test compression for FPGAs. In Proceedings of the International Test Conference. 1--9.Google ScholarGoogle Scholar
  22. Toutounchi, S. and Lai, A. 2002. FPGA test and coverage. In Proceedings of the International Test Conference. 599--607. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Xilinx. 2009. Virtex-6 FPGA configuration user guide. UG360 (v2.0), Xilinx, Inc.Google ScholarGoogle Scholar

Index Terms

  1. Test compression for dynamically reconfigurable processors

      Recommendations

      Comments

      Login options

      Check if you have access through your login credentials or your institution to get full access on this article.

      Sign in

      Full Access

      • Published in

        cover image ACM Transactions on Reconfigurable Technology and Systems
        ACM Transactions on Reconfigurable Technology and Systems  Volume 4, Issue 4
        December 2011
        179 pages
        ISSN:1936-7406
        EISSN:1936-7414
        DOI:10.1145/2068716
        Issue’s Table of Contents

        Copyright © 2011 ACM

        Publisher

        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 28 December 2011
        • Accepted: 1 March 2011
        • Revised: 1 December 2010
        • Received: 1 October 2010
        Published in trets Volume 4, Issue 4

        Permissions

        Request permissions about this article.

        Request Permissions

        Check for updates

        Qualifiers

        • research-article
        • Research
        • Refereed
      • Article Metrics

        • Downloads (Last 12 months)0
        • Downloads (Last 6 weeks)0

        Other Metrics

      PDF Format

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader
      About Cookies On This Site

      We use cookies to ensure that we give you the best experience on our website.

      Learn more

      Got it!