Abstract
Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the power and performance of the entire system. Further, the memory subsystem constitutes a major part (typically up to 70%) of the silicon area for the current day SoC. In this article, we address the on-chip memory architecture exploration for DSP processors which are organized as multiple memory banks, where banks can be single/dual ported with non-uniform bank sizes. In this paper we propose two different methods for physical memory architecture exploration and identify the strengths and applicability of these methods in a systematic way. Both methods address the memory architecture exploration for a given target application by considering the application's data access characteristics and generates a set of Pareto-optimal design points that are interesting from a power, performance and VLSI area perspective. To the best of our knowledge, this is the first comprehensive work on memory space exploration at physical memory level that integrates data layout and memory exploration to address the system objectives from both hardware design and application software development perspective. Further we propose an automatic framework that explores the design space identifying 100's of Pareto-optimal design points within a few hours of running on a standard desktop configuration.
- Acosta, R. 2006. Embedded systems gallery. http://www.eetimes.com/design/automotive-design/4004589/Verification-challenges-of-embedded-memory-devices.Google Scholar
- Ascia, G., Catania, V., and Palesi, M. 2001. Parameterised system design based on genetic algorithms. In Proceedings of the ACM 2nd International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES).Google Scholar
- Avissar, O., Barua, R., and Stewart, D. 2001. Heterogeneous memory management for embedded systems. In Proceedings of the ACM 2nd International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES). Google Scholar
Digital Library
- Benini, L., Macchiarulo, L., Macii, A., and Poncino, M. 2002. Layout driven memory synthesis for embededed systems-on-chip. In Proceedings of the ACM 3rd International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES).Google Scholar
- Cao, Y., Tomiyama, H., Okuma, T., and Yasuura, H. 2002. Data memory design considering effective bitwidth for low energy embedded systems. In Proceedings of ISSS. Google Scholar
Digital Library
- Deb, K. 1996. Multi-objective evolutionary algorithms: Introducing bias among pareto-optimal solutions. Tech. rep., IIT Kanpur.Google Scholar
- Hiser, J. D. and Davidson, J. W. 2004. Embarc: an efficient memory bank assignment algorithm for retargetable compilers. In Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems. ACM. 182--191. Google Scholar
Digital Library
- Jha, P. K., and Dutt, N. D. 1997. Library mapping for memories. In Proceedings of EuroDesign. Google Scholar
Digital Library
- Ko, M., and Bhattacharyya, S. 2003. Data partitioning for DSP software synthesis. In Proceedings of the International Workshop on Software and Compilers for Embedded Processors.Google Scholar
- Leupers, R., and Kotte, D. 2001. Variable partitioning for dual memory bank DSPs. In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP). Google Scholar
Digital Library
- Palesi, M. and Givargis, T. 2002. Multi-objective design space exploration using genetic algorithms. In Proceedings of the International Workshop on Hardware/Software Codesign (CODES). Google Scholar
Digital Library
- Panda, P., Dutt, N., and Nicolau, A. 1998. Memory Issues in Embedded Systems-on-Chip:Optimizations and Exploration. Kluwer Academic Publishers, Norwell, MA. Google Scholar
Digital Library
- Panda, P., Dutt, N., and Nicolau, A. 2000. On-chip vs. off-chip memory: The data partitioning problem in embedded processor-based systems. ACM Trans. Design Autom. Electron. Syst. 5, 3, 682--704. Google Scholar
Digital Library
- Rajesh Kumar, T.S., Govindarajan, R., and Ravikumar, C.P. 2003. Optimal code and data layout for embedded systems. In Proceedings of the International Conference on VLSI Design. Google Scholar
Digital Library
- Rajesh Kumar, T.S. 2008. On-Chip Memory Architecture Exploration of Embedded System on Chip . Ph.D. Thesis, Supercomputer Education & Research Centre, Indian Institute of Science, Bangalore 560012, India.Google Scholar
- Saghir, M., Chow, P., and Lee, C. 1996. Exploiting dual data-memory banks in digital signal processors. In Proceedings of the 7th International Conference Architectural Support for Programming Languages and Operating Systems. 234--243. Google Scholar
Digital Library
- Schmit, H. and Thomas, D. 1995. Array mapping in behavioral synthesis. In Proceedings of ISSS. Google Scholar
Digital Library
- SEMATECH. 2001. International technology roadmap for semiconductors. SEMATECH, Austin TX.Google Scholar
- Seo, J., Kim, T., and Panda, P. 2002. An integrated algorithm for memory allocation and assignment in high-level synthesis. In Proceedings of the 39th Design Automation Conference. 608--611. Google Scholar
Digital Library
- Seo, J., Kim, T., and Panda, P. 2003. Memory allocation and mapping in high-level synthesis: an integrated approach. IEEE Trans. VLSI Syst. 11, 5. Google Scholar
Digital Library
- Sjodin, J., and Platen, C. 2001. Storage allocation for embedded processors. In Proceedings of the ACM 2nd International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES). Google Scholar
Digital Library
- Sriram, S., and Bhattacharyya, S. S. 2000. Embedded Multiprocecssors: Scheduling and Synchronization. Embedded Computer Systems. Google Scholar
Digital Library
- Sundaram, A., and Pande, S. 1998. An efficient data partitioning method for limited memory embedded systems. In Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems (in conjunction with PLDI'98. 205--218. Google Scholar
Digital Library
- Szymanek, R., Catthoor, F., and Kuchcinski, K. 2004. Time-energy design space exploration for multi-layer memory architectures. In Proceedings of Design Automation and Test Europe. Google Scholar
Digital Library
- Texas Instruments 2001. TMS320C55x DSP CPU Reference Guide. Texas Instruments, http://dspvillage.ti.com/docs/dspproducthome.html.Google Scholar
- Udayakumaran, S., Dominguez, A., and Barua, R. 2005. Dynamic allocation for scratch-pad memory using compile-time decisions. ACM Trans. Embedd. Comput. Syst. 5, 1--33. Google Scholar
Digital Library
Index Terms
On-chip memory architecture exploration framework for DSP processor-based embedded system on chip
Recommendations
Dynamic Sharing of On-Chip Scratchpad Memory on Embedded Platforms
ISED '12: Proceedings of the 2012 International Symposium on Electronic System DesignAs more and more functions are integrated on a System-On-Chip (SoC), the number of on-chip peripherals is increasing sharply. Most of these peripheral functions use an internal scratchpad memory for temporary storage of data. Hence, the area and power ...
Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency
DAC '09: Proceedings of the 46th Annual Design Automation ConferenceMemory access latency and memory-related operations are often the performance bottleneck in parallel applications. In this paper, we present a concept of active memory operations which is an on-chip network transaction that operates based on the ...
On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches
Traditionally, design-space exploration for systems-on-chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, a shift from ...






Comments