Abstract
Modern real-time streaming applications are increasingly implemented on multiprocessor systems-on-chip (MPSoC). The implementation, as well as the verification of real-time applications executing on MPSoCs, are difficult tasks, however. A major challenge is the performance analysis of MPSoCs, which is required for early design space exploration and final system verification. Simulation-based methods are not well-suited for this purpose, due to long runtimes and non-exhaustive corner-case coverage. To overcome these limitations, formal performance analysis methods that provide guarantees for meeting real-time constraints have been developed. Embedding formal performance analysis into the MPSoC design cycle requires the generation of a faithful analysis model and its calibration with the system-specific parameters. In this article, a design flow that automates these steps is presented. In particular, we integrate modular performance analysis (MPA) into the distributed operation layer (DOL) MPSoC programming environment. The result is an MPSoC software design flow that allows for automatically generating the system implementation, together with an analysis model for system verification.
- Balsamo, S., Marco, A. D., Inverardi, P., and Simeoni, M. 2004. Model-based performance prediction in software development: A survey. IEEE Trans. Softw. Eng. 30, 5, 295--310. Google Scholar
Digital Library
- Benini, L., Bertozzi, D., Alessandro, B., Menichelli, F., and Olivieri, M. 2005. {MPARM: Exploring the multiprocessor soc design space with SystemC. J. VLSI Signal Process. 41, 169--182. Google Scholar
Digital Library
- Black, B. and Shen, J. P. 1998. Calibration of microprocessor performance models. Comput. 31, 5, 59--65. Google Scholar
Digital Library
- Chakraborty, S., Künzli, S., and Thiele, L. 2003. A general framework for analyzing system properties in platform-based embedded system design. In Proceedings of the Design, Automation and Test in Europe (DATE). 190--195. Google Scholar
Digital Library
- Densmore, D., Sangiovanni-Vincentelli, A., and Passerone, R. 2006. A platform-based taxonomy for ESL design. IEEE Design Test Comput. 23, 5, 359--374. Google Scholar
Digital Library
- Gerstlauer, A., Haubelt, C., Pimentel, A. D., Stefanov, T., Gajski, D. D., and Teich, J. 2009. Electronic system-level synthesis methodologies. IEEE Trans. Comput.-Aid. Design Integr. Circuits Syst. 28, 10, 1517--1530. Google Scholar
Digital Library
- González Harbour, M., Gutiérrez García, J. J., Palencia Gutiérrez, J. C., and Drake Moyano, J. M. 2001. MAST: Modeling and analysis suite for real time applications. In Proceedings of the Euromicro Conference on Real-Time Systems. 125--134. Google Scholar
Digital Library
- Haid, W., Keller, M., Huang, K., Bacivarov, I., and Thiele, L. 2009. Generation and calibration of compositional performance analysis models for multiprocessor systems. In Proceedings of the International Conference on Systems, Architectures, Modeling and Simulation (IC-SAMOS). 92--99. Google Scholar
Digital Library
- Haid, W. and Thiele, L. 2007. Complex task activation schemes in system level performance analysis. In Proceedings of the International Conference on HW/SW Codesign and System Synthesis (CODES/ISSS). 173--178. Google Scholar
Digital Library
- Henia, R., Hamann, A., Jersak, M., Racu, R., Richter, K., and Ernst, R. 2005. System level performance analysis — The SymTA/S approach. IEE Proc.: Comput. Digital Tech. 152, 2, 148--166.Google Scholar
Cross Ref
- Jersak, M., Richter, K., and Ernst, R. 2005. Performance analysis for complex embedded systems. Int. J. Embedd. Syst. 1, 1--2, 33--49.Google Scholar
- Jonsson, B., Perathoner, S., Thiele, L., and Yi, W. 2008. Cyclic dependencies in modular performance analysis. In Proceedings of the International Conference on Embedded Software (EMSOFT). 179--188. Google Scholar
Digital Library
- Kahle, J., Day, M., Hofstee, H., Johns, C., Maeurer, T., and Shippy, D. 2005. Introduction to the cell multiprocessor. IBM J. Res. Develop. 49, 4/5, 589--604. Google Scholar
Digital Library
- Kahn, G. 1974. The semantics of a simple language for parallel programming. In Proceedings of the IFIP Congress. 471--475.Google Scholar
- Kangas, T., Kukkala, P., Orsila, H., Salminen, E., Hännikäinen, M., and Hämäläinen, T. D. 2006. UML-based multiprocessor soc design framework. ACM Trans. Embedd. Comput. Syst. 5, 2, 281--320. Google Scholar
Digital Library
- Künzli, S., Poletti, F., Benini, L., and Thiele, L. 2006. Combining simulation and formal methods for system-level performance analysis. In Proceedings of the Design, Automation and Test in Europe (DATE). 236--241. Google Scholar
Digital Library
- Lahiri, K., Raghunathan, A., and Dey, S. 2001. System-level performance analysis for designing on-chip communication architectures. IEEE Trans. Comput.-Aid. Design Integr. Circuits Syst. 20, 6, 768--783. Google Scholar
Digital Library
- Lampka, K., Perathoner, S., and Thiele, L. 2010. Analytic real-time analysis and timed automata: A hybrid methodology for the performance analysis of embedded real-time systems. Des. Autom. Embedd. Syst. 14, 3, 193--227.Google Scholar
Digital Library
- Le Boudec, J.-Y. and Thiran, P. 2001. Network Calculus—A Theory of Deterministic Queuing Systems for the Internet. Lecture Notes in Computer Science, vol. 2050. Springer-Verlag, Berlin, Germany. Google Scholar
Digital Library
- Lee, E. A. and Messerschmitt, D. G. 1987. Synchronous data flow. Proc. IEEE 75, 9, 1235--1245.Google Scholar
Cross Ref
- Lee, E. A. and Parks, T. M. 1995. Dataflow Process Networks. Proc. IEEE 83, 5, 773--799.Google Scholar
- Maxiaguine, A., Künzli, S., and Thiele, L. 2004. Workload characterization model for tasks with variable execution demand. In Proceedings of the Design, Automation and Test in Europe (DATE). 1040--1045. Google Scholar
Digital Library
- Paolucci, P., Jerraya, A., Leupers, R., Thiele, and Vicini, P. 2006. SHAPES: A tiled scalable software hardware architecture platform for embedded systems. In Proceedings of the International Conference HW/SW Codesign and System Synthesis (CODES/ISSS). 167--172. Google Scholar
Digital Library
- Pellizzoni, R. and Caccamo, M. 2007. Toward the predictable integration of real-time COTS-based systems. In Proceedings of the Real-Time Systems Symposium (RTSS). 73--82. Google Scholar
Digital Library
- Perathoner, S., Rein, T., Thiele, L., Lampka, K., and Rox, J. 2010. Modeling structured event streams in system level performance analysis. In Proceedings of the ACM Conference on Languages, Compilers and Tools for Embedded Systems (LCTES). Google Scholar
Digital Library
- Perathoner, S., Wandeler, E., Thiele, L., Hamann, A., Schliecker, S., Henia, R., Racu, R., Ernst, R., and González Harbour, M. 2009. Influence of different abstractions on the performance analysis of distributed hard real-time systems. Des. Autom. Embedd. Syst. 13, 1, 27--49.Google Scholar
Digital Library
- Petriu, D., Shousha, C., and Jalnapurkar, A. 2000. Architecture-based performance analysis applied to a telecommunication system. IEEE Trans. Softw. Eng. 26, 11, 1049--1065. Google Scholar
Digital Library
- Pimentel, A., Erbas, C., and Polstra, S. 2006. A systematic approach to exploring embedded system architectures at multiple abstraction levels. IEEE Trans. Comput. 55, 2, 99--112. Google Scholar
Digital Library
- Pimentel, A. D., Thompson, M., Polstra, S., and Erbas, C. 2008. Calibration of abstract performance models for system system-level design space exploration. J. Signal Process. Syst. 50, 2, 99--114. Google Scholar
Digital Library
- RTEMS Steering Committee. 2010. RTEMS. http://www.rtems.com.Google Scholar
- Thiele, L., Bacivarov, I., Haid, W., and Huang, K. 2007. Mapping-applications to tiled multiprocessor embedded systems. In Proceedings of the International Conference on Application of Concurrency to System Design (ACSD). 29--40. Google Scholar
Digital Library
- Thiele, L. and Stoimenov, N. 2009. Modular performance analysis of cyclic dataflow graphs. In Proceedings of the International Conference on Embedded Software (EMSOFT). 127--136. Google Scholar
Digital Library
- Thies, W., Karczmarek, M., and Amarasinghe, S. 2002. StreamIt: A language for streaming applications. In Proceedings of the 11th International Conference on Compiler Construction. 179--196. Google Scholar
Digital Library
- Viehl, A., Schönwald, T., Bringmann, O., and Rosenstiehl, W. 2006. Formal performance analysis and simulation of UML/SysML models for ESL design. In Proceedings of the Design, Automation and Test in Europe (DATE). 242--247. Google Scholar
Digital Library
- Wandeler, E. and Thiele, L. 2006a. Interface-based design of real-time systems with hierarchical scheduling. In Proceedings of the Real-Time and Embedded Technology and Applications Symposium (RTAS). 243--252. Google Scholar
Digital Library
- Wandeler, E. and Thiele, L. 2006b. Optimal TDMA time slot and cycle length allocation for hard real-time systems. In Proceedings of the Asia and South Pacific Conference on Design Automation (ASP-DAC). 479--484. Google Scholar
Digital Library
- Wandeler, E. and Thiele, L. 2006c. Real-Time Calculus (RTC) toolbox. http://www.mpa.ethz.ch/Rtctoolbox.Google Scholar
- Wandeler, E., Thiele, L., Verhoef, M., and Lieverse, P. 2006. System architecture evaluation using modular performance analysis: A case study. Int. J. Softw. Tools Technol. Transfer 8, 6, 649--667. Google Scholar
Digital Library
- Wilhelm, R., Engblom, J., Ermedahl, A., Holsti, N., Thesing, S., Whalley, D., Bernat, G., Ferdinand, C., Heckmann, R., Mitra, T., Mueller, F., Puaut, I., Puschner, P., Staschulat, J., and Stenström, P. 2008. The worst-case execution time problem — Overview of methods and survey of tools. ACM Trans. Embedd. Comput. Syst. 7, 3, 36:1--36:53. Google Scholar
Digital Library
- Woodside, M. 2007. From annotated software designs (UML SPT/MARTE) to model formalisms. Lecture Notes in Computer Science, vol. 4486. Springer-Verlag, Berlin, Germany, 429--467. Google Scholar
Digital Library
Index Terms
Embedding formal performance analysis into the design cycle of MPSoCs for real-time streaming applications
Recommendations
Throughput-oriented NoC topology generation and analysis for high performance SoCs
This paper presents a new approach to the design and analysis of NoC topologies which is based on the transaction-oriented communication methods of on-chip components. We propose two algorithms that attempt to meet the communication requirement of an on-...
"It's a small world after all": noc performance optimization via long-range link insertion
Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a ...
Finitary Real-Time Calculus: Efficient Performance Analysis of Distributed Embedded Systems
RTSS '13: Proceedings of the 2013 IEEE 34th Real-Time Systems SymposiumReal-Time Calculus (RTC) is a powerful framework to analyze real-time performance of distributed embedded systems. However, RTC may run into serious analysis efficiency problems when applied to systems of large scale and/or with complex timing parameter ...






Comments