Abstract
In recent years, efficient dynamic reconfiguration techniques have been widely employed for system optimization. Dynamic cache reconfiguration is a promising approach for reducing energy consumption as well as for improving overall system performance. It is a major challenge to introduce cache reconfiguration into real-time multitasking systems, since dynamic analysis may adversely affect tasks with timing constraints. This article presents a novel approach for implementing cache reconfiguration in soft real-time systems by efficiently leveraging static analysis during runtime to minimize energy while maintaining the same service level. To the best of our knowledge, this is the first attempt to integrate dynamic cache reconfiguration in real-time scheduling techniques. Our experimental results using a wide variety of applications have demonstrated that our approach can significantly reduce the cache energy consumption in soft real-time systems (up to 74%).
- Andersson, B., Bletsas, K., and Baruah, S. 2008. Scheduling arbitrary-deadline sporadic task systems on multiprocessors. In Proceedings of the Real-Time Systems Symposium. 385--394. Google Scholar
Digital Library
- Benini, L., Bogliolo, R., and Micheli, G. D. 2000. A survey of design techniques for system-level dynamic power management. IEEE Trans. VLSI Syst. 8, 299--316. Google Scholar
Digital Library
- Burger, D., Austin, T. M., and Bennett, S. 1996. Evaluating future microprocessors: The simplescalar tool set. Tech. rep., University of Wisconsin-Madison, Madison, WI.Google Scholar
- Buttazzo, G. 1995. Hard Real-Time Computing Systems. Kluwer, Berlin, Heidelberg.Google Scholar
- EEMBC. 2000. EEMBC, The Embedded Microprocessor Benchmark Consortium. http://www.eembc.org.Google Scholar
- Gordon-Ross, A. and Vahid, F. 2004. Automatic tuning of two-level caches to embedded applications. In Proceedings of the Design, Automation and Test in Europe Conference. 208--213. Google Scholar
Digital Library
- Gordon-Ross, A., Vahid, F., and Dutt, N. 2005. Fast configurable-cache tuning with a unified second-level cache. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED’05). 323--326. Google Scholar
Digital Library
- Gordon-Ross, A., Viana, P., Vahid, F., Najjar, W., and Barros, E. 2007. A one-shot configurable-cache tuner for improved energy and performance. In Proceedings of the Design, Automation and Test in Europe Conference. 755--760. Google Scholar
Digital Library
- Hennessy, J. and Patterson, D. 2003. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, Waltham, MA. Google Scholar
Digital Library
- Hong, I., Kirovski, D., Qu, G., Potkonjak, M., and Srivastava, M. B. 1999. Power optimization of variable-voltage core-based systems. IEEE Trans. Comput.-Aided Des. Integr. Cir. Syst. 18, 1702--1714. Google Scholar
Digital Library
- Hong, S., Yoo, S., Jin, H., Choi, K., Kong, J., and Eo, S. 2006. Runtime distribution-aware dynamic voltage scaling. In Proceedings of the International Conference on Computer-Aided Design. 587--594. Google Scholar
Digital Library
- HP. 2008. CACTI, HP Laboratories Palo Alto, CACTI 5.3. http://www.hpl.hp.com/.Google Scholar
- Hu, J. and Marculescu, R. 2004. Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints. In Proceedings of the Design, Automation and Test in Europe Conference. 234--239. Google Scholar
Digital Library
- Jejurikar, R. and Gupta, R. 2005. Dynamic slack reclamation with procrastination scheduling in real-time embedded systems. In Proceedings of the Design Automation Conference. 111--116. Google Scholar
Digital Library
- Jejurikar, R. and Gupta, R. 2006. Energy-aware task scheduling with task synchronization for embedded real-time systems. IEEE Trans. Comput.-Aided Des. Integr. Cir. Syst. 25, 1024--1037. Google Scholar
Digital Library
- Jejurikar, R., Pereira, C., and Gupta, R. K. 2004. Leakage aware dynamic voltage scaling for real-time embedded systems. In Proceedings of the Design Automation Conference. 275--280. Google Scholar
Digital Library
- Kim, H., Somani, A. K., and Tyagi, A. 2000. A reconfigurable multi-function computing cache architecture. In Proceedings of the International Symposium on Field Programmable Gate Arrays. 85--94. Google Scholar
Digital Library
- Lee, C., Potkonjak, M., and Mangione-smith, W. H. 1997. Mediabench: A tool for evaluating and synthesizing multimedia and communications systems. In Proceedings of the International Symposium on Microarchitecture. 330--335. Google Scholar
Digital Library
- Leung, L., Tsui, C., and Hu, X. S. 2005. Exploiting dynamic workload variation in low energy preemptive task scheduling. In Proceedings of the Design, Automation and Test in Europe Conference. 634--639. Google Scholar
Digital Library
- Liu, J. 2000. Real-Time Systems. Prentice Hall, Upper Saddle River, NJ.Google Scholar
- Malik, A., Moyer, B., and Cermak, D. 2000. A low power unified cache architecture providing power and performance flexibility. In Proceedings of the International Symposium on Low Power Electronics and Design. 241--243. Google Scholar
Digital Library
- Modarressi, M., Hessabi, S., and Goudarzi, M. 2006. A reconfigurable cache architecture for object-oriented embedded systems. In Proceedings of the Canadian Conference on Electrical and Computer Engineering. 959--962.Google Scholar
- Nacul, A. C. and Givargis, T. 2004. Dynamic voltage and cache reconfiguration for low power. In Proceedings of the Design, Automation and Test in Europe Conference. 21376. Google Scholar
Digital Library
- Oh, S., Kim, J., Kim, S., and Kyung, C. 2008. Task partitioning algorithm for intra-task dynamic voltage scaling. In Proceedings of the International Symposium on Circuits and Systems. 1228--1231.Google Scholar
- Puant, I. 2002. Cache analysis vs static cache locking for schedulability analysis in multitasking real-time systems. In Proceedings of the International Workshop on Worst-Case Execution Time Analysis.Google Scholar
- Puant, I. and Decotigny, D. 2002. Low-complexity algorithms for static cache locking in multitasking hard real-time systems. In Proceedings of the IEEE Real-Time Systems Symposium. 114--125. Google Scholar
Digital Library
- Puant, I. and Pais, C. 2007. Scratchpad memories vs locked caches in hard real-time systems: A quantitative comparison. In Proceedings of the Design, Automation and Test in Europe Conference. 1484--1489. Google Scholar
Digital Library
- Quan, G. and Hu, X. S. 2007. Energy efficient dvs schedule for fixed-priority real-time systems. ACM Trans. Des. Autom. Electron. Syst. 6, 1--30.Google Scholar
- Rong, P. and Pedram, M. 2008. Energy-aware task scheduling and dynamic voltage scaling in a real-time system. J. Low Power Electron. 4, 1--10.Google Scholar
Cross Ref
- Segars, S. 2001. Low power design techniques for microprocessors. In Proceedings of the International Solid State Circuit Conference.Google Scholar
- Seo, J., Kim, T., and Chung, K. 2004. Profile-based optimal intra-task voltage scheduling for hard real-time applications. In Proceedings of the Design Automation Conference. 87--92. Google Scholar
Digital Library
- Settle, A., Connors, D., and Gibert, E. 2006. A dynamically reconfigurable cache for multithreaded processors. J. Embed. Comput. 2, 221--233. Google Scholar
Digital Library
- Sherwood, T., Perelman, E., Hamerly, G., Sair, S., and Calder, B. 2003. Discovering and exploiting program phases. In Proceedings of the International Symposium on Microarchitecture. 84--93.Google Scholar
- Shin, D., Kim, J., and Lee, S. 2001. Low-energy intra-task voltage scheduling using static timing analysis. In Proceedings of the Design Automation Conference. 438--443. Google Scholar
Digital Library
- Sprunt, B. 1990. Aperiodic task scheduling for real-time systems. Ph.D. dissertation, Carnegie Mellon University, Pittsburg, PA. Google Scholar
Digital Library
- Staschulat, J., Schliecker, S., and Ernst, R. 2005. Scheduling analysis of real-time systems with precise modeling of cache related preemption delay. In Proceedings of the Euromicro Conference on Real-Time Systems. 41--48. Google Scholar
Digital Library
- Tan, Y. and Mooney, V. J. 2007. Timing analysis for preemptive multitasking real-time systems with caches. ACM Trans. Embed. Comput. Syst. 6, 7. Google Scholar
Digital Library
- Varma, A., Debes, E., Kozintsev, I., and Jacob, B. 2005. Instruction-level power dissipation in the intel xscale embedded microprocessor. In Proceedings of the SPIE 17th Annual Symposium on Electronic Imaging Science & Technology.Google Scholar
- Wang, W. and Mishra, P. 2009. Dynamic reconfiguration of two-level caches in soft real-time embedded systems. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI. 145--150. Google Scholar
Digital Library
- Wolfe, A. 1993. Software-based cache partitioning for real-time applications. In Proceedings of the International Workshop on Responsive Computer Systems.Google Scholar
- Zhang, C., Vahid, F., and Lysecky, R. 2004. A self-tuning cache architecture for embedded systems. In Proceedings of the Design, Automation and Test in Europe Conference. Google Scholar
Digital Library
- Zhang, C., Vahid, F., and Najjar, W. 2005. A highly configurable cache for low energy embedded systems. ACM Trans. Embed. Comput. Syst. 6, 362--387. Google Scholar
Digital Library
- Zhang, S., Chatha, K., and Konjevod, G. 2007. Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules. In Proceedings of the International Symposium on Low Power Electronics and Design. 225--230. Google Scholar
Digital Library
- Zhong, X. and Xu, C. 2005. Energy-aware modeling and scheduling of real-time tasks for dynamic voltage scaling. In Proceedings of the International Real-Time Systems Symposium. 366--375. Google Scholar
Digital Library
Index Terms
Dynamic Cache Reconfiguration for Soft Real-Time Systems
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