Abstract
An efficient word-level finite field multiplier using redundant representation is proposed. The proposed multiplier has a significantly higher speed, compared to previously proposed word-level architectures using either redundant representation or optimal normal basis type I, at the expense of moderately higher area complexity. Furthermore, the new design out-performs other similar proposals when considering the product of area and delay as a measure of performance. ASIC Realization of the proposed design using TSMC’s .18 um CMOS technology for the binary field size of 163 is also presented.
- 0.18μm TSMC CMOS Technology 1999. Standard cell library. Available through Canadian Microelectronics Corporation.Google Scholar
- Agnew, G., Mullin, R., and Vanstone, S. 1993. An implementation of elliptic curve cryptosystems over f2155. IEEE J. Select. Areas Commun. 11, 5, 804--813. Google Scholar
Digital Library
- Berlekamp, E. 1968. Algebraic Coding Theory. McGraw-Hill, New York, NY.Google Scholar
- Drolet, G. 1998. A new representation of elements of finite fields gf(2m) yielding small complexity arithmetic circuits. IEEE Trans. Comput. 47, 9, 938--946. Google Scholar
Digital Library
- Gao, L. and Sobelman, G. 2000. Improved vlsi designs for multiplication and inversion in gf(2m) over normal bases. In Proceedings of the 13th Annual IEEE International ASIC/SOC Conference. IEEE, Los Alamitos, CA, 97--101.Google Scholar
- Hasan, M. and Bhargava, V. 1995. Architecture for a low complexity rate-adaptive reed-solomon encoder. IEEE Trans. Comput. 44, 7, 938--942. Google Scholar
Digital Library
- IEEE Std 1363-2000. 2000. IEEE standard specifications for public-key cryptography. http://standards.ieee.org/findstds/standard/1363-2000.html.Google Scholar
- Lidl, R. and Niederreiter, H. 1997. Introduction to Finite Fields and Their Applications 2nd Ed. Cambridge University Press, Cambridge.Google Scholar
- Massey, J. L. and Omura, J. K. 1986. Computational method and apparatus for finite field arithmetic. U.S. patent 4587627, filed September 14, 1982, and issued May 6, 1986.Google Scholar
- Mastrovito, E. 1988. Vlsi designs for multiplication over finite fields gf(2m). In Proceedings of the 6th International Conference on Applied Algebra, Algebraic Algorithms and Error-Correcting Codes. 297--309. Google Scholar
Digital Library
- Menezes, A., van Oorschot, P., and Vanstone, S. 1996. Handbook of Applied Cryptography. CRC-Press, Boca Raton, FL. Google Scholar
Digital Library
- Mullin, R., Onyszchuk, I., Vanstone, S. A., and Wilson, R. 1988. Optimal normal bases in gf(pn). Disc. Appl. Math. 22, 2, 149--161. Google Scholar
Digital Library
- Namin, A., Leboeuf, K., Muscedere, R., Wu, H., and Ahmadi, M. 2010. High speed hardware implementation of a serial-in parallel-out finite field multiplier using reordered normal basis. IET Circuits, Devices & Systems 4, 2, 168--179.Google Scholar
- Namin, A. H., Wu, H., and Ahmadi, M. 2007. Comb architectures for finite field multiplication in f2m. IEEE Trans. Comput. 56, 7, 909--916. Google Scholar
Digital Library
- Namin, A. H., Wu, H., and Ahmadi, M. 2008. A new finite field multiplier using redundant representation. IEEE Trans. Comput. 57, 5, 716--720. Google Scholar
Digital Library
- Pak-Keung, L., Chiu-Sing, C., Cbeong-Fat, C., and Kong-Pang, P. 2003. A low power asynchronous gf(2173) alu for elliptic curve crypto-processor. In Proceedings of the International Symposium on Circuits and Systems. 337--340.Google Scholar
- Reyhani-Masoleh, A. and Hasan, M. A. 2003. Efficient digit-serial normal basis multipliers over gf(2m). IEEE Trans. Comput. 52, 4, 428--439. Google Scholar
Digital Library
- Reyhani-Masoleh, A. and Hasan, M. A. 2005. Low complexity word-level sequential normal basis multipliers. IEEE Trans. Comput. 54, 2, 98--110. Google Scholar
Digital Library
- Silverman, J. H. 1999. Fast multiplication in finite fields gf(2n). In Proceedings of the 1st International Workshop on Cryptographic Hardware and Embedded Systems. 122--134. Google Scholar
Digital Library
- Tang, W., Wu, H., and Ahmadi, M. 2005. Vlsi implementation of bit-parallel word-serial multiplier in gf(2233). In Proceedings of the 3rd International IEEE-NEWCAS Conference. IEEE, Los Alamitos, CA, 399--402.Google Scholar
- Uyemura, J. 1999. CMOS Logic Circuit Design. Kluwer Academic Pub., Norwell, MA. Google Scholar
Digital Library
- Wu, H., Hasan, M. A., Blake, I. F., and Gao, S. 2002. Finite field multiplier using redundant representation. IEEE Trans. Comput. 51, 11, 1306--1316. Google Scholar
Digital Library
Index Terms
An Efficient Finite Field Multiplier Using Redundant Representation
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