skip to main content
research-article

WCET-aware data selection and allocation for scratchpad memory

Authors Info & Claims
Published:12 June 2012Publication History
Skip Abstract Section

Abstract

In embedded systems, SPM (scratchpad memory) is an attractive alternative to cache memory due to its lower energy consumption and higher predictability of program execution. This paper studies the problem of placing variables of a program into an SPM such that its WCET (worst-case execution time) is minimized. We propose an efficient dynamic approach that comprises two novel heuristics. The first heuristic iteratively selects a most beneficial variable as an SPM resident candidate based on its impact on the k longest paths of the program. The second heuristic incrementally allocates each SPM resident candidate to the SPM based on graph coloring and acyclic graph orientation. We have evaluated our approach by comparing with an ILP-based approach and a longest-path-based greedy approach using the eight benchmarks selected from Powerstone and Mälardalen WCET Benchmark suites under three different SPM configurations. Our approach achieves up to 21% and 43% improvements in WCET reduction over the ILP-based approach and the greedy approach, respectively.

References

  1. Angiolini, F., Menichelli, F., Ferrero, A., Benini, L., and Olivieri, M. A post-compiler approach to scratchpad mapping of code. In Proceedings of the 2004 International Cconference on Compilers, Architecture and Synthesis for Embedded Systems (2004), pp. 259--267. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Deverge, J.-F., and Puaut, I. WCET-directed dynamic scratchpad memory allocation of data. In Proceedings of the 19th Euromicro Conference on Real-Time Systems (2007), pp. 179--190. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Egger, B., Lee, J., and Shin, H. Dynamic scratchpad memory management for code in portable systems with an MMU. ACM Transactions on Embedded Computing Systems 7, 2 (2008), 11:1--11:38. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Falk, H., and Kleinsorge, J. C. Optimal static WCET-aware scratchpad allocation of program code. In Proceedings of the 46th Annual Design Automation Conference (2009), pp. 732--737. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Falk, H., Plazar, S., and Theiling, H. Compile-time decided instruction cache locking using worst-case execution paths. In Proceedings of the 5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (2007), pp. 143--148. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Francesco, P., Marchal, P., Atienza, D., Benini, L., Catthoor, F., and Mendias, J. M. An integrated hardware/software approach for run-time scratchpad management. In Proceedings of the 41st annual Design Automation Conference (2004), pp. 238--243. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Goldberg, A., Wang, T., and Zimmermann, D. Applications of feasible path analysis to program testing. In Proceedings of the 1994 ACM SIGSOFT International Symposium on Software Testing and Analysis (1994), pp. 80--94. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Gustafsson, J., Betts, A., Ermedahl, A., and Lisper, B. The Mälardalen WCET benchmarks -- past, present and future. In Proceedings of the 10th International Workshop on Worst-Case Execution Time Analysis (2010), pp. 137--147.Google ScholarGoogle Scholar
  9. Hennessy, J. L., and Patterson, D. A. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Janapsatya, A., Ignjatovic, A., and Parameswaran, S. A novel instruction scratchpad memory optimization method based on concomitance metric. In Proceedings of the 2006 Asia and South Pacific Design Automation Conference (2006), pp. 612--617. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Janapsatya, A., Parameswaran, S., and Ignjatovic, A. Hardware/software managed scratchpad memory for embedded system. In Proceedings of the 2004 IEEE/ACM International Conference on Computer-Aided Design (2004), pp. 370--377. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Kandemir, M. T., Ramanujam, J., Irwin, M. J., Vijaykrishnan, N., Kadayif, I., and Parikh, A. Dynamic management of scratch-pad memory space. In Proceedings of the 38th annual Design Automation Conference (2001), pp. 690--695. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Li, L., Feng, H., and Xue, J. Compiler-directed scratchpad memory management via graph coloring. ACM Transactions on Architecture and Code Optimization 6, 3 (2009), 9:1--9:17. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Li, L., Nguyen, Q. H., and Xue, J. Scratchpad allocation for data aggregates in superperfect graphs. In Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (2007), pp. 207--26. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Li, L., Xue, J., and Knoop, J. Scratchpad memory allocation for data aggregates via interval coloring in superperfect graphs. ACM Transactions on Embedded Computing Systems 10, 2 (2011), 28:1--28:42. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Li, X., Liang, Y., Mitra, T., and Roychoudhury, A. Chronos: A timing analyzer for embedded software. Science of Computer Programming 69, 1--3 (2007), 56--67. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Liu, T., Li, M., and Xue, C. J. Minimizing WCET for real-time embedded systems via static instruction cache locking. In Proceedings of the 15th IEEE Symposium on Real-Time and Embedded Technology and Applications (2009), pp. 35--44. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Palem, K. V., and Simons, B. B. Scheduling time-critical instructions on risc machines. ACM Transactions on Programming Languages and Systems 15, 4 (1993), 632--658. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Plazar, S., Falk, H., Kleinsorge, J. C., and Marwedel, P. WCET-aware static locking of instruction caches. In Proceedings of the International Symposium on Code Generation and Optimization (2012), pp. 44--52. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Puaut, I., and Pais, C. Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison. In Proceedings of the conference on Design, Automation and Test in Europe (2007), pp. 1484--1489. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Scott, J., Lee, L. H., Arends, J., and Moyer, B. Designing the low-power M*CORE architecture. In Proceedings of IEEE Power Driven Micro Architecture Workshop (1998), pp. 145--150.Google ScholarGoogle Scholar
  22. Suhendra, V., Mitra, T., Roychoudhury, A., and Chen, T. WCET centric data allocation to scratchpad memory. In Proceedings of the 26th IEEE International Real-Time Systems Symposium (2005), pp. 223--232. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Suhendra, V., Mitra, T., Roychoudhury, A., and Chen, T. Efficient detection and exploitation of infeasible paths for software timing analysis. In Proceedings of the 43rd annual Design Automation Conference (2006), pp. 358--363. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. Udayakumaran, S., and Barua, R. Compiler-decided dynamic memory allocation for scratch-pad based embedded systems. In Proceedings of the 2003 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (2003), pp. 276--286. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. Vera, X., Lisper, B., and Xue, J. Data cache locking for higher program predictability. In Proceedings of the 2003 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems (2003), pp. 272--282. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. Vera, X., Lisper, B., and Xue, J. Data cache locking for tight timing calculations. ACM Transactions on Embedded Computing Systems 7, 1 (2007), 4:1--4:38. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. Verma, M., and Marwedel, P. Overlay techniques for scratchpad memories in low power embedded processors. IEEE Transactions on Very Large Scale Integration Systems 14, 8 (2006), 802--815. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. Wu, H., Xue, J., and Parameswaran, S. Optimal WCET-aware code selection for scratchpad memory. In Proceedings of the 10th ACM International Conference on Embedded Software (2010), pp. 59--68. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Yang, X., Wang, L., Xue, J., Deng, Y., and Zhang, Y. Comparability graph coloring for optimizing utilization of stream register files in stream processors. In Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (2009), pp. 111--120. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. WCET-aware data selection and allocation for scratchpad memory

        Recommendations

        Comments

        Login options

        Check if you have access through your login credentials or your institution to get full access on this article.

        Sign in

        Full Access

        PDF Format

        View or Download as a PDF file.

        PDF

        eReader

        View online with eReader.

        eReader
        About Cookies On This Site

        We use cookies to ensure that we give you the best experience on our website.

        Learn more

        Got it!