Abstract
Variants of dataflow specification models are widely used to synthesize streaming applications for distributed-memory parallel processors. We argue that current practice of specifying streaming applications using rigid dataflow models, implicitly prohibits a number of platform oriented optimizations and hence limits portability and scalability with respect to number of processors. We motivate Functionally-cOnsistent stRucturally-MalLEabe Streaming Specification, dubbed FORMLESS, which refers to raising the abstraction level beyond fixed-structure dataflow to address its portability and scalability limitations. To demonstrate the potential of the idea, we develop a design space exploration scheme to customize the application specification to better fit the target platform. Experiments with several common streaming case studies demonstrate improved portability and scalability over conventional dataflow specification models, and confirm the effectiveness of our approach.
- S. Battacharyya, E. Lee, and P. Murthy. Software synthesis from dataflow graphs. Kluwer Academic Publishers, 1996. Google Scholar
Digital Library
- S. Stuijk, M. Geilen, and T. Basten. Throughput-buffering trade-off exploration for cyclo-static and synchronous dataflow graphs. IEEE Transactions on Computers, 57(10):1331--1345, 2008. Google Scholar
Digital Library
- M. Gordon. Compiler techniques for scalable performance of stream programs on multicore architectures. PhD thesis, Massachusetts Institute of Technology, 2010. Google Scholar
Digital Library
- Andy D. Pimentel et al. Exploring embedded-systems architectures with Artemis. IEEE Computer, 34(11):57--63, 2001. Google Scholar
Digital Library
- A. Sangiovanni-Vincentelli et al. Benefits and challenges for platform-based design. Design Automation Conference (DAC), pages 409--414, 2004. Google Scholar
Digital Library
- D. Truong et al. A 167--processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling. Symposium on VLSI Circuits, 2008.Google Scholar
- S. Bell et al. TILE64 processor: A 64-core SoC with mesh interconnect. International Solid-State Circuits Conference (ISSCC), 2008.Google Scholar
- E. Lee and D. Messerschmitt. Synchronous data flow. Proceedings of the IEEE, 75(9):1235--1245, 1987.Google Scholar
Cross Ref
- M. Geilen and T. Basten. Reactive process networks. International Conference on Embedded Software (EMSOFT), pages 137--146, 2004. Google Scholar
Digital Library
- J. Colaço, A. Girault, G. Hamon, and M. Pouzet. Towards a higher-order synchronous data-flow language. International Conference on Embedded Software (EMSOFT), pages 230--239, 2004. Google Scholar
Digital Library
- W. Taha. A gentle introduction to multi-stage programming. Domain-Specific Program Generation, Lecture Notes in Computer Science (LNCS), 2004.Google Scholar
- J. Adam Cataldo. The power of higher-order composition languages in system design. PhD thesis, University of California, Berkeley, 2006.Google Scholar
- Marc Geilen. Reduction techniques for synchronous dataflow graphs. Design Automation Conference (DAC), 2009. Google Scholar
Digital Library
- B. Bhattacharya and S. Bhattacharyya. Parameterized dataflow modeling for DSP systems. IEEE Transactions on Signal Processing, 49(10):2408--2421, 2001. Google Scholar
Digital Library
- B.D. Theelen et al. A scenario-aware data flow model for combined long-run average and worst-case performance analysis. Formal Methods and Models in CoDesign, 2006.Google Scholar
Digital Library
- Maarten H. Wiggers, Marco J. G. Bekooij, and Gerard J. M. Smit. Buffer capacity computation for throughput constrained streaming applications with data-dependent inter-task communication. IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2008. Google Scholar
Digital Library
- Pascal Fradet, Alain Girault, and Peter Poplavko. A schedulable parametric data-flow MoC. Design, Automation, and Test in Europe (DATE), 2012.Google Scholar
- J. Nickolls et al. Scalable parallel programming with CUDA. ACM Queue, 6:40--53, March 2008. Google Scholar
Digital Library
- CUDA C best practices guide, chapter 4.4. March 2011.Google Scholar
- G. Karypis and V. Kumar. METIS 4.0: Unstructured graph partitioning and sparse matrix ordering system. Technical report, CS Dept., University of Minnesota, Minneapolis, 1998.Google Scholar
- T. Mohsenin, D. Truong, and B. Baas. Multi-split-row threshold decoding implementations for LDPC codes. International Symposium on Circuits and Systems (ISCAS), 2009.Google Scholar
Cross Ref
- Po-Kuan Huang, Matin Hashemi, and Soheil Ghiasi. System-level performance estimation for application-specific mpsoc interconnect synthesis. Symposium on Application Specific Processors (SASP), 2008. Google Scholar
Digital Library
- Matin Hashemi. Automated Software Synthesis for Streaming Applications on Embedded Manycore Processors. PhD thesis, University of California, Davis, 2011. Chapter 4. Google Scholar
Digital Library
Recommendations
FORMLESS: scalable utilization of embedded manycores in streaming applications
LCTES '12: Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded SystemsVariants of dataflow specification models are widely used to synthesize streaming applications for distributed-memory parallel processors. We argue that current practice of specifying streaming applications using rigid dataflow models, implicitly ...
Multidimensional Dataflow Graph Modeling and Mapping for Efficient GPU Implementation
SIPS '12: Proceedings of the 2012 IEEE Workshop on Signal Processing SystemsMultidimensional synchronous dataflow (MDSDF) provides an effective model of computation for a variety of multidimensional DSP systems that have static dataflow structures. In this paper, we develop new methods for optimized implementation of MDSDF ...
Performance Model for Parallel Matrix Multiplication with Dryad: Dataflow Graph Runtime
CGC '12: Proceedings of the 2012 Second International Conference on Cloud and Green ComputingIn order to meet the big data challenge of today's society, several parallel execution models on distributed memory architectures have been proposed: MapReduce, Iterative MapReduce, graph processing, and dataflow graph processing. Dryad is a distributed ...






Comments