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"Smart" design space sampling to predict Pareto-optimal solutions

Published:12 June 2012Publication History
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Abstract

Many high-level synthesis tools offer degrees of freedom in mapping high-level specifications to Register-Transfer Level descriptions. These choices do not affect the functional behavior but span a design space of different cost-performance tradeoffs. In this paper we present a novel machine learning-based approach that efficiently determines the Pareto-optimal designs while only sampling and synthesizing a fraction of the design space. The approach combines three key components: (1) A regression model based on Gaussian processes to predict area and throughput based on synthesis training data. (2) A "smart" sampling strategy, GP-PUCB, to iteratively refine the model by carefully selecting the next design to synthesize to maximize progress. (3) A stopping criterion based on assessing the accuracy of the model without access to complete synthesis data. We demonstrate the effectiveness of our approach using IP generators for discrete Fourier transforms and sorting networks. However, our algorithm is not specific to this application and can be applied to a wide range of Pareto front prediction problems.

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            • Published in

              cover image ACM SIGPLAN Notices
              ACM SIGPLAN Notices  Volume 47, Issue 5
              LCTES '12
              MAY 2012
              152 pages
              ISSN:0362-1340
              EISSN:1558-1160
              DOI:10.1145/2345141
              Issue’s Table of Contents
              • cover image ACM Conferences
                LCTES '12: Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems
                June 2012
                153 pages
                ISBN:9781450312127
                DOI:10.1145/2248418

              Copyright © 2012 ACM

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              • Published: 12 June 2012

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