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Variability-tolerant workload allocation for MPSoC energy minimization under real-time constraints

Published:01 January 2013Publication History
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Abstract

Sub-50nm CMOS technologies are affected by significant variability, which causes power and performance variations among nominally similar cores in MPSoC platforms. This undesired heterogeneity threatens execution predictability and energy efficiency. We propose two techniques to allocate sets of barrier-synchronized tasks. The first technique models allocation as an ILP and achieves optimal results, but requires an offline solver. The second technique adopts a two-stage heuristic approach, and it can be adapted to work online. We tested our approach on the virtual prototype of a next-generation industrial multicore platform. Experimental results demonstrate that our approach minimizes deadline violations while increasing energy efficiency.

References

  1. Akyol, E. and van der Schaar, M. 2007. Complexity model based proactive dynamic voltage scaling for video decoding systems. IEEE Trans. Multimedia 9, 7, 1475--1492. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Drake, A., Senger, R., Singh, H., Carpenter, G., and James, N. 2008. Dynamic measurement of critical-path timing. In Proceedings of the IEEE International Conference on Integrated Circuit Design and Technology (ICICDT). 249--252.Google ScholarGoogle Scholar
  3. Faraboschi, P., Brown, G., Fisher, J. A., Desoli, G., and Homewood, F. 2000. Lx: A technology platform for customizable vliw embedded processing. In Proceedings of ISCA. 203--213. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Flamand, E. 2009. Strategic directions toward multicore application specific computing. In Proceedings of Design, Automation and Test in Europe. 1266--1266. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Herbert, S. and Marculescu, D. 2008. Characterizing chip-multiprocessor variability-tolerance. In Proceedings of the 45th Annual Design Automation Conference (DAC). ACM, New York, NY, 313--318. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Hong, S. and et al. 2009. Process variation aware thread mapping for chip multiprocessors. In Proceedings of Design, Automation and Test in Europe. 821--826. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Huang, L., Yuan, F., and Xu, Q. 2009. Lifetime reliability-aware task allocation and scheduling for mpsoc platforms. In Proceedings of Design, Automation and Test in Europe. 51--56. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Kollig, P., Henriksson, T., and Osborne, C. 2009. Heterogeneous multicore platforms for consumer multimedia applications. In Proceedings of Design, Automation and Test in Europe. 1254--1259. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Papanicolaou, A. and et al. 2007. At tape-out: Can system yield in terms of timing/energy specifications be predicted? In Proceedings of the IEEE Custom Integrated Circuits Conference (CICC). 773--778.Google ScholarGoogle Scholar
  10. Paterna, F., Benini, L., Paparieilo, F., Desoli, G., Acqvaviva, A., and Olivieri, M. 2009. Adaptive idleness distribution for non-uniform aging tolerance in multiprocessor systems-on-chip. In Proceedings of the Design, Automation and Test in Europe. 906--909. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Rebaud, B., Belleville, M., Beigne, E., Robert, M., Maurine, P., and Azemard, N. 2009. An innovative timing slack monitor for variation tolerant circuits. In Proceedingd of the IEEE International IC Design and Technology conference (ICICDT). 215--218.Google ScholarGoogle Scholar
  12. Teodorescu, R. and Torrellas, J. 2008. Variation-aware application scheduling and power management for chip multiprocessors. SIGARCH Comput. Archit. News 36, 3, 363--374. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Tiwari, A. and Torrellas, J. 2008. Facelift: Hiding and slowing down aging in multicores. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture (MICRO). 129--140. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. VAM. Vam - variability aware modeling. http://www.imec.be/ScientificReport/SR2007/html/1384291.html.Google ScholarGoogle Scholar
  15. Wang, F., Nicopoulos, C., Wu, X., Xie, Y., and Vijay Krishnan, N. 2007. Variation-aware task allocation and scheduling for MPsoC. In Proceedings of the MPsoC International Conference on Computer-Aided Design. 598--603. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Winter, J. and Albonesi, D. 2008. Scheduling algorithms for unpredictably heterogeneous cmp architectures. In Proceedings of the 38th International Conference on Dependable Systems and Networks (DSN). 42--51.Google ScholarGoogle Scholar
  17. Yi, Y., Han, W., Zhao, X., Erdogan, A. T., and Arslan, T. 2009. An ilp formulation for task mapping and scheduling on multi-core architectures. In Proceedings of DATE. 33--38. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Zhang, L., Bai, L., Dick, R. P., Shang, L., and Joseph, R. 2009. Process variation characterization of chip-level multiprocessors. In Proceedings of the Design Automation Conference. 694--697. Google ScholarGoogle ScholarDigital LibraryDigital Library

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