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Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers

Published:01 October 2012Publication History
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Abstract

Load value speculation has long been proposed as a method to hide the latency of memory accesses. It has seen very limited use in actual processors, often due to the high overhead of reexecuting misspeculated computations. We present PreCoRe, a framework capable of generating application-specific microarchitectures supporting load value speculation on reconfigurable computers. The article examines the lightweight speculation and replay mechanisms, the architecture of the actual data value prediction units as well as the impact on the nonspeculative parts of the memory system. In experiments, using PreCoRe has achieved speedups of up to 2.48 times over nonspeculative implementations.

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            • Published in

              cover image ACM Transactions on Reconfigurable Technology and Systems
              ACM Transactions on Reconfigurable Technology and Systems  Volume 5, Issue 3
              October 2012
              102 pages
              ISSN:1936-7406
              EISSN:1936-7414
              DOI:10.1145/2362374
              Issue’s Table of Contents

              Copyright © 2012 ACM

              Publisher

              Association for Computing Machinery

              New York, NY, United States

              Publication History

              • Published: 1 October 2012
              • Accepted: 1 August 2012
              • Revised: 1 May 2012
              • Received: 1 September 2011
              Published in trets Volume 5, Issue 3

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