Abstract

With the shift to many-core chip multiprocessors (CMPs), a critical issue is how to effectively coordinate and manage the execution of applications and hardware resources to overcome performance, power consumption, and reliability challenges stemming from hardware and application variations inherent in this new computing environment. Effective resource and application management on CMPs requires consideration of user/application/hardware-specific requirements and dynamic adaption of management decisions based on the actual run-time environment. However, designing an algorithm to manage resources and applications that can dynamically adapt based on the run-time environment is difficult because most resource and application management and monitoring facilities are only available at the operating system level. This paper presents REEact, an infrastructure that provides the capability to specify user-level management policies with dynamic adaptation. REEact is a virtual execution environment that provides a framework and core services to quickly enable the design of custom management policies for dynamically managing resources and applications. To demonstrate the capabilities and usefulness of REEact, this paper describes three case studies--each illustrating the use of REEact to apply a specific dynamic management policy on a real CMP. Through these case studies, we demonstrate that REEact can effectively and efficiently implement policies to dynamically manage resources and adapt application execution.
- Java(TM) 2 Platform Standard Edition 5.0 API Specification. http://java.sun.com/j2se/1.5.0/docs/api/.Google Scholar
- Intel 64 and IA-32 architecture software developer's manual, 2011.Google Scholar
- T. E. Anderson, B. N. Bershad, E. D. Lazowska, and H. M. Levy. Scheduler activations: effective kernel support for the user-level management of parallelism. In Proc. of the Thirteenth ACM Symposium on Operating Systems Principles, pages 95--109, 1991. Google Scholar
Digital Library
- P. Barham, B. Dragovic, K. Fraser, S. Hand, T. Harris, A. Ho, R. Neugebauer, I. Pratt, and A. Warfield. Xen and the art of virtualization. In Proc. of the Nineteenth ACM Symposium on Operating Systems Principles, pages 164--177, 2003. Google Scholar
Digital Library
- ach, and Singhania}2009-Baumann-SOSPA. Baumann, P. Barham, P.-E. Dagand, T. Harris, R. Isaacs, S. Peter, T. Roscoe, A. Schüpbach, and A. Singhania. The multikernel: a new OS architecture for scalable multicore systems. In Proc. of the 22nd ACM Symposium on Operating Systems Principles, pages 29--44, 2009. Google Scholar
Digital Library
- C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC benchmark suite: characterization and architectural implications. In Proc. of the 17th Int'l Conf. on Parallel Architectures and Compilation Techniques, pages 72--81, 2008. Google Scholar
Digital Library
- S. Chen, B. Falsafi, P. B. Gibbons, M. Kozuch, T. C. Mowry, R. Teodorescu, A. Ailamaki, L. Fix, G. R. Ganger, B. Lin, and S. W. Schlosser. Log-based architectures for general-purpose monitoring of deployed code. In 1st Workshop on Architectural and System Support for Improving Software Dependability, pages 63--65, 2006. Google Scholar
Digital Library
- S. Chen, P. B. Gibbons, M. Kozuch, V. Liaskovitis, A. Ailamaki, G. E. Blelloch, B. Falsafi, L. Fix, N. Hardavellas, T. C. Mowry, and C. Wilkerson. Scheduling threads for constructive cache sharing on CMPs. In Proc. of the Nineteenth Annual ACM Symposium on Parallel Algorithms and Architectures, pages 105--115, 2007. Google Scholar
Digital Library
- J. del Cuvillo. Breaking away from the OS Shadow: A Program Execution Model Aware Thread Virtual Machine for Multicore Architectures. PhD thesis, University of Delaware, Newark, DE, USA, 2008.Google Scholar
- E. Duesterwald, C. Cascaval, and S. Dwarkadas. Characterizing and Predicting Program Behavior and its Variability. In Proc. of the 12th Int'l Conf. on Parallel Architectures and Compilation Techniques, pages 220--231, 2003. Google Scholar
Digital Library
- E. Ebrahimi, O. Mutlu, C. J. Lee, and Y. N. Patt. Coordinated control of multiple prefetchers in multi-core systems. In Proc. of the 42nd Annual IEEE/ACM Int'l Symposium on Microarchitecture, pages 316--326, 2009. Google Scholar
Digital Library
- E. Ebrahimi, C. J. Lee, O. Mutlu, and Y. N. Patt. Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems. In Proc. of the Fifteenth Edition of ASPLOS on Architectural Support for Programming Languages and Operating Systems, pages 335--346, 2010. Google Scholar
Digital Library
- D. R. Engler, M. F. Kaashoek, and J. O'Toole, Jr. Exokernel: an operating system architecture for application-level resource management. In Proc. of the Fifteenth ACM Symposium on Operating Systems Principles, pages 251--266, 1995. Google Scholar
Digital Library
- S. Eranian. Perfmon2: A flexible performance monitoring interface for Linux. In Ottawa Linux Symposium, pages 269--288, 2006.Google Scholar
- H. Esmaeilzadeh, T. Cao, Y. Xi, S. M. Blackburn, and K. S. McKinley. Looking back on the language and hardware revolutions: measured power, performance, and scaling. In Proc. of the Sixteenth Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, pages 319--332, 2011. Google Scholar
Digital Library
- I. Hur and C. Lin. Memory Prefetching Using Adaptive Stream Detection. In Proc. of the 39th Annual IEEE/ACM Int'l Symposium on Microarchitecture, pages 397--408, 2006. Google Scholar
Digital Library
- L. Jin and S. Cho. SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors. In Proc. of the 2009 18th Int'l Conf. on Parallel Architectures and Compilation Techniques, pages 361--371, 2009. Google Scholar
Digital Library
- M. Kadin, S. Reda, and A. Uht. Central vs. distributed dynamic thermal management for multi-core processors: which one is better? In Proc. of the 19th ACM Great Lakes Symposium on VLSI, pages 137--140, 2009. Google Scholar
Digital Library
- S. Kim, D. Chandra, and Y. Solihin. Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture. In Proc. of the 13th Int'l Conf. on Parallel Architectures and Compilation Techniques, pages 111--122, 2004. Google Scholar
Digital Library
- E. Kursun, G. Reinman, S. Sair, A. Shayesteh, and T. Sherwood. Low-Overhead Core Swapping for Thermal Management. In Workshop on Power-Aware Computer Systems, 2004. Google Scholar
Digital Library
- J. Lee, H. Wu, M. Ravichandran, and N. Clark. Thread tailor: dynamically weaving threads together for efficient, adaptive parallel applications. In Proc. of the 37th Annual Int'l Symposium on Computer Architecture, pages 270--279, 2010. Google Scholar
Digital Library
- K. J. Nesbit, J. Laudon, and J. E. Smith. Virtual private machines: A resource abstraction. Technical report, In University of Wisconsin - Madison, ECE TR, 2007.Google Scholar
- D. Nikolopoulos, G. Back, J. Tripathi, and M. Curtis-Maury. VT-ASOS: Holistic system software customization for many cores. In IEEE Int'l Symposium on Parallel and Distributed Processing, pages 1--5, 2008.Google Scholar
- A. Noll, A. Gal, and M. Franz. CellVM: A Homogeneous Virtual Machine Runtime System for a Heterogeneous Single-Chip Multiprocessor. In Workshop on Cell Systems and Applications, 2008.Google Scholar
- C. Pheatt. Intel® threading building blocks. J. Comput. Small Coll., 23 (4): 298--298, 2008. ISSN 1937--4771. Google Scholar
Digital Library
- S. Srinath, O. Mutlu, H. Kim, and Y. N. Patt. Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. In Proc. of the IEEE 13th Int'l Symposium on High Performance Computer Architecture, pages 63--74, 2007. Google Scholar
Digital Library
- U. Steinberg and B. Kauer. Towards a scalable multiprocessor user-level environment. In Workshop on Isolation and Integration for Dependable Systems, 2010.Google Scholar
- D. K. Tam, R. Azimi, L. B. Soares, and M. Stumm. RapidMRC: Approximating L2 miss rate curves on commodity systems for online optimizations. In Proc. of the 14th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, pages 121--132, 2009. Google Scholar
Digital Library
- R. Teodorescu and J. Torrellas. Variation-aware application scheduling and power management for chip multiprocessors. In Proc. of the 35th Annual Int'l Symposium on Computer Architecture, pages 363--374, 2008. Google Scholar
Digital Library
- J. Winter and D. Albonesi. Scheduling algorithms for unpredictably heterogeneous CMP architectures. In IEEE Int'l Conf. on Dependable Systems and Networks With FTCS and DCC, pages 42 --51, 2008.Google Scholar
- J. Yang, X. Zhou, M. Chrobak, Y. Zhang, and L. Jin. Dynamic Thermal Management through Task Scheduling. In IEEE Int'l Symposium on Performance Analysis of Systems and Software, pages 191--201, 2008. Google Scholar
Digital Library
- I. Yeo, C. C. Liu, and E. J. Kim. Predictive dynamic thermal management for multicore systems. In Proc. of the 45th Annual Design Automation Conference, pages 734--739, 2008. Google Scholar
Digital Library
- X. Zhang, S. Dwarkadas, and K. Shen. Hardware execution throttling for multi-core resource management. In Proc. of the 2009 Conf. on USENIX Annual Technical Conference, pages 23--23, 2009. Google Scholar
Digital Library
- S. Zhuravlev, S. Blagodurov, and A. Fedorova. Addressing shared resource contention in multicore processors via scheduling. In Proc. of the Fifteenth Edition of ASPLOS on Architectural Support for Programming Languages and Operating Systems, pages 129--142, 2010. Google Scholar
Digital Library
- S. Zhuravlev, S. Blagodurov, and A. Fedorova. AKULA: a toolset for experimenting and developing thread placement algorithms on multicore systems. In Proc. of the 19th Int'l Conf. on Parallel Architectures and Compilation Techniques, pages 249--260, 2010. Google Scholar
Digital Library
Index Terms
REEact: a customizable virtual execution manager for multicore platforms
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