skip to main content
research-article

Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform

Published:01 December 2012Publication History
Skip Abstract Section

Abstract

Power is an important issue limiting the applicability of Field Programmable Gate Arrays (FPGAs) since it is considered to be up to one order of magnitude higher than in ASICs. Recently, dynamic reconfiguration in FPGAs has emerged as a viable technique able to achieve power and cost reductions by time-multiplexing the required functionality at runtime. In this article, the applicability of Adaptive Voltage Scaling (AVS) to FPGAs is considered together with dynamic reconfiguration of logic and clock management resources to further improve the power profile of these devices. AVS is a popular power-saving technique in ASICs that enables a device to regulate its own voltage and frequency based on workload, fabrication, and operating conditions. The resulting processing platform exploits the available application-dependent timing margins to achieve a power reduction up to 85% operating at 0.58 volts compared with operating at a nominal voltage of 1 volt. The results also show that the energy requirements at 0.58 volts are aproximately five times lower compared with nominal voltage and this can be explained by the approximate cubic relation of static energy with voltage and the fact that the static component dominates power consumption in the considered FPGA devices.

References

  1. Altera. 2010. Increasing design functionality with partial and dynamic reconfiguration in 28-nm fpgas. http://www.altera.com/literature/wp/wp-01137-stxv-dynamic-partial-reconfig.pdf.Google ScholarGoogle Scholar
  2. Anderson, J. H., Najm, F. N., and Tuan, T. 2004. Active leakage power optimization for fpgas. In Proceedings of the ACM SIGDA 12th International Symposium on Field Programmable Gate Arrays (FPGA’04). ACM Press, New York, 33--41. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Calhoun, B., Honore, F., and Chandrakasan, A. 2003. Design methodology for fine-grained leakage control in mtcmos. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED’03). 104--109. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Chow, C., Tsui, L., Leong, P., Luk, W., and Wilton, S. 2005. Dynamic voltage scaling for commercial fpgas. In Proceedings of the IEEE International Conference on Field Programmable Technology. 173--180.Google ScholarGoogle Scholar
  5. Dhar, S. and Mortensen, G. 2005. Closed-Loop adaptive supply voltage scaling controller for low-power embedded processors. In Proceedings of the IEEE Technical, Professional and Student Development Workshop. 6--11.Google ScholarGoogle Scholar
  6. Dye, D. 2011. Partial reconfiguration of virtex fpgas in ise12. http://www.xilinx.com/support/documentation/white_papers/wp374_Partial_Reconfig_Xilinx_FPGAs.pdf.Google ScholarGoogle Scholar
  7. Gaisler, A. 2010a. Grlib ip core user’s manual. http://www.gaisler.com/products/grlib/grip.pdf.Google ScholarGoogle Scholar
  8. Gaisler, A. 2010b. Grlib ip library user’s manual. http://gaisler.com/products/grlib/grip.pdf.Google ScholarGoogle Scholar
  9. Gayasen, A., Tsai, Y., Vijaykrishnan, N., Kandemir, M., Irwin, M. J., and Tuan, T. 2004. Reducing leakage energy in fpgas using region-constrained placement. In Proceedings of the ACM SIGDA 12th International Symposium on Field Programmable Gate Arrays (FPGA’04). ACM Press, New York, 51--58. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. George, V., Zhang, H., and Rabaey, J. 1999. The design of a low energy fpga. In Proceedings of the International Symposium on Low Power Electronics and Design (ISPLED’99). 188--193. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Hsu, C.-H. and Kremer, U. 2003. The design, implementation, and evaluation of a compiler algorithm for cpu energy reduction. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI’03). ACM Press, New York, 38--48. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Iyer, A. and Marculescu, D. 2002. Power and performance evaluation of globally asynchronous locally synchronous processors. In Proceedings of the 29th Annual International Symposium on Computer Architecture. 158--168. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Klein, P. A. M. and Philofsky, B. 2008. Virtex-5 fpga system power design considerations. http://www.xilinx.com/support/documentation/white_papers/wp285.pdf.Google ScholarGoogle Scholar
  14. Kuon, I. and Rose, J. 2007. Measuring the gap between fpgas and asics. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 26, 2, 203--215. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Lamoureux, J. and Wilton, S. 2003. On the interaction between power-aware fpga cad algorithms. In Proceedings of the International Conference on Computer Aided Design (ICCAD’03). 701--708. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Lamoureux, J. and Wilton, S. 2007. Clock-Aware placement for fpgas. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’07). 124--131.Google ScholarGoogle Scholar
  17. Li, F., Lin, Y., and He, L. 2004a. Fpga power reduction using configurable dual-vdd. In Proceedings of the 41st Design Automation Conference (DAC’04). 735--740. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Li, F., Lin, Y., and He, L. 2004b. Vdd programmability to reduce fpga interconnect power. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD’04). 760--765. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Li, F., Lin, Y., He, L., and Cong, J. 2004c. Low-Power fpga using pre-defined dual-vdd/dual-vt fabrics. In Proceedings of the ACM SIGDA 12th International Symposium on Field Programmable Gate Arrays (FPGA’04). ACM Press, New York, 42--50. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Liu, M., Kuehn, W., Lu, Z., and Jantsch, A. 2009. Run-Time partial reconfiguration speed investigation and architectural design space exploration. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’09). 498--502.Google ScholarGoogle Scholar
  21. McDonald, E. 2008. Runtime fpga partial reconfiguration. In Proceedings of the IEEE Aerospace Conference. 1--7.Google ScholarGoogle ScholarCross RefCross Ref
  22. Nabina, A. and Nunez-Yanez, J. L. 2010. Dynamic reconfiguration optimisation with streaming data decompression. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’10). IEEE Computer Society, 602--607. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Nunez-Yanez, J., Chouliaras, V., and Gaisler, J. 2007. Dynamic voltage scaling in a fpga-based system-on-chip. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’07). 459--462.Google ScholarGoogle Scholar
  24. Nunez-Yanez, J., Hung, E., and Chouliaras, V. 2008. A configurable and programmable motion estimation processor for the h.264 video codec. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL’08). 149--154.Google ScholarGoogle Scholar
  25. Rahman, A. and Polavarapuv, V. 2004. Evaluation of low-leakage design techniques for field programmable gate arrays. In Proceedings of the ACM SIGDA 12th International Symposium on Field Programmable Gate Arrays (FPGA’04). ACM Press, New York, 23--30. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. Rahman, A., Das, S., Tuan, T., and Rahut, A. 2005. Heterogeneous routing architecture for low-power fpga fabric. In Proceedings of the IEEE Custom Integrated Circuits Conference. 183--186.Google ScholarGoogle Scholar
  27. Ryan, J. and Calhoun, B. 2010. A sub-threshold fpga with low-swing dual-vdd interconnect in 90nm cmos. In Proceedings of the IEEE Custom Integrated Circuits Conference (CICC’10). IEEE 1--4.Google ScholarGoogle Scholar
  28. Talpes, E. and Marculescu, D. 2005. Toward a multiple clock/voltage island design style for power-aware processors. IEEE Trans. VLSI Syst. 13, 591--603. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Weiser, M., Welch, B., Demers, A., and Shenker, S. 1994. Scheduling for reduced cpu energy. In Proceedings of the 1st USENIX Conference on Operating Systems Design and Implementation (OSDI’94). Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. Xilinx. 2010a. Virtex-5 fpga data sheet: Dc and switching characteristics. http://www.xilinx.com/support/documentation/data_sheets/ds202.pdf.Google ScholarGoogle Scholar
  31. Xilinx. 2010b. Virtex-5 fpga user guide. http://www.xilinx.com/support/documentation/user_guides/ug190.pdf.Google ScholarGoogle Scholar

Index Terms

  1. Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in

    Full Access

    • Published in

      cover image ACM Transactions on Reconfigurable Technology and Systems
      ACM Transactions on Reconfigurable Technology and Systems  Volume 5, Issue 4
      December 2012
      95 pages
      ISSN:1936-7406
      EISSN:1936-7414
      DOI:10.1145/2392616
      Issue’s Table of Contents

      Copyright © 2012 ACM

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 1 December 2012
      • Accepted: 1 June 2012
      • Revised: 1 April 2012
      • Received: 1 October 2011
      Published in trets Volume 5, Issue 4

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • research-article
      • Research
      • Refereed

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader
    About Cookies On This Site

    We use cookies to ensure that we give you the best experience on our website.

    Learn more

    Got it!