Abstract
The sensitivity of a cache replacement policy expresses to what extent the execution history may influence the number of cache hits and misses during program execution. We present an algorithm to compute the sensitivity of a replacement policy. We have implemented this algorithm in a tool called Relacs that can handle a large class of replacement policies including LRU, FIFO, PLRU, and MRU. Sensitivity properties obtained with Relacs demonstrate that the execution history can have a strong impact on the number of cache hits and misses if FIFO, PLRU, or MRU is used. A simple model of execution time is used to evaluate the impact of cache sensitivity on measured execution times. The model shows that measured execution times may strongly underestimate the worst-case execution time for FIFO, PLRU, and MRU.
- Ahuja, R. K., Magnanti, T. L., and Orlin, J. B. 1993. Network Flows: Theory, Algorithms, and Applications. Prentice-Hall, Inc., Upper Saddle River, NJ. Google Scholar
Digital Library
- Al-Zoubi, H., Milenkovic, A., and Milenkovic, M. 2004. Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite. In Proceedings of the ACM 42nd Annual Southeast Regional Conference. ACM Press, New York, NY, 267--272. Google Scholar
Digital Library
- Berg, C. 2006. PLRU cache domino effects. In Proceedings of the 6th International Workshop on Worst-Case Execution Time (WCET) Analysis. F. Mueller, Ed., Internationales Begegnungs- und Forschungszentrum für Informatik (IBFI), Schloss Dagstuhl, Germany.Google Scholar
- Bernat, G., Colin, A., and Petters, S. M. 2002. WCET analysis of probabilistic hard real-time systems. In Proceedings of the 23rd IEEE Real-Time Systems Symposium (RTSS'02). IEEE Computer Society, Los Alamitos, CA, 279. Google Scholar
Digital Library
- Deverge, J.-F. and Puaut, I. 2005. Safe measurement-based WCET estimation. In Proceedings of the 5th International Workshop on Worst-Case Execution Time (WCET) Analysis. R. Wilhelm, Ed., Internationales Begegnungs- und Forschungszentrum für Informatik (IBFI), Schloss Dagstuhl, Germany.Google Scholar
- Eklöv, D., Nikoleris, N., Black-Schaffer, D., and Hagersten, E. 2011. Cache pirating: Measuring the curse of the shared cache. In Proceedings of ICPP. 165--175. Google Scholar
Digital Library
- Engblom, J. and Jonsson, B. 2002. Processor pipelines and their properties for static WCET analysis. In Proceedings of the 2nd International Conference on Embedded Software (EMSOFT'02). Springer-Verlag, 334--348. Google Scholar
Digital Library
- Ferdinand, C., Heckmann, R., Langenbach, M., Martin, F., Schmidt, M., Theiling, H., Thesing, S., and Wilhelm, R. 2001. Reliable and precise WCET determination for a real-life processor. In Proceedings of the Embedded Software Workshop. Vol. 2211, 469--485. Google Scholar
Digital Library
- Heckmann, R., Langenbach, M., Thesing, S., and Wilhelm, R. 2003. The influence of processor architecture on the design and the results of WCET tools. Proc. IEEE 91, 7, 1038--1054. Google Scholar
Cross Ref
- Hennessy, J. L. and Patterson, D. A. 1996. Computer Architecture: A Quantitative Approach 2nd Ed., Morgan Kaufmann. Google Scholar
Digital Library
- Lawler, E. 1966. Optimal cycles in doubly weighted linear graphs. In Proceedings of the International Symposium on Theory of Graphs. 209--213.Google Scholar
- Petters, S. M. 2002. Worst case execution time estimation for advanced processor architectures. Ph.D. thesis, Technische Universität München, Munich, Germany.Google Scholar
- Puaut, I. and Decotigny, D. 2002. Low-complexity algorithms for static cache locking in multitasking hard real-time systems. In Proceedings of the 23rd IEEE Real-Time Systems Symposium (RTSS'02). IEEE Computer Society, Los Alamitos, CA, 114. Google Scholar
Digital Library
- Reineke, J. 2008. Caches in WCET analysis. Ph.D. thesis, Universität des Saarlandes.Google Scholar
- Reineke, J. and Grund, D. 2008. Relative competitive analysis of cache replacement policies. In Proceedings of the ACM SIGPLAN-SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems. ACM, New York, NY, 51--60. Google Scholar
Digital Library
- Reineke, J., Grund, D., Berg, C., and Wilhelm, R. 2007. Timing predictability of cache replacement policies. Real-Time Syst. 37, 2, 99--122. Google Scholar
Digital Library
- Schlickling, M. and Pister, M. 2010. Semi-automatic derivation of timing models for WCET analysis. In Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems. ACM, 67--76. Google Scholar
Digital Library
- Silberschatz, A., Galvin, P. B., and Gagne, G. 2005. Operating System Concepts. Vol. 2nd. Addison-Wesley. Google Scholar
Digital Library
- Theiling, H., Ferdinand, C., and Wilhelm, R. 2000. Fast and precise WCET prediction by separate cache and path analyses. Real-Time Syst. 18, 2/3. Google Scholar
Digital Library
- Vera, X., Lisper, B., and Xue, J. 2003. Data cache locking for higher program predictability. SIGMETRICS Perform. Eval. Rev. 31, 1, 272--282. Google Scholar
Digital Library
- Wenzel, I. 2006. Measurement-based timing analysis of superscalar processors. Ph.D. thesis, Technische Universität Wien, Institut für Technische Informatik.Google Scholar
- Wilhelm, R., Engblom, J., Ermedahl, A., Holsti, N., Thesing, S., Whalley, D. B., Bernat, G., Ferdinand, C., Heckmann, R., Mitra, T., Mueller, F., Puaut, I., Puschner, P. P., Staschulat, J., and Stenström, P. 2008. The worst-case execution-time problem - overview of methods and survey of tools. ACM Trans. Embed. Comput. Syst. 7, 3. Google Scholar
Digital Library
- Wilhelm, R., Grund, D., Reineke, J., Schlickling, M., Pister, M., and Ferdinand, C. 2009. Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems. IEEE Trans. CAD Integrat. Circuits Syst. 28, 7, 966--978. Google Scholar
Digital Library
Index Terms
- Sensitivity of cache replacement policies
Recommendations
Relative competitive analysis of cache replacement policies
LCTES '08Caches are commonly employed to hide the latency gap between memory and the CPU by exploiting locality in memory accesses. On today's architectures a cache miss may cost several hundred CPU cycles.
In order to fulfill stringent performance requirements, ...
Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite
ACM-SE 42: Proceedings of the 42nd annual Southeast regional conferenceReplacement policy, one of the key factors determining the effectiveness of a cache, becomes even more important with latest technological trends toward highly associative caches. The state-of-the-art processors employ various policies such as Random, ...
Relative competitive analysis of cache replacement policies
LCTES '08: Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systemsCaches are commonly employed to hide the latency gap between memory and the CPU by exploiting locality in memory accesses. On today's architectures a cache miss may cost several hundred CPU cycles.
In order to fulfill stringent performance requirements, ...





Comments