Abstract
Reliability in embedded systems is crucial for many application domains. Especially, for safety critical application, as they can be found in the automotive and avionic domain, a high reliability has to be ensured. The technology in chip production undergoes a steady shrinking process from nowadays 25 nanometers. It is proven that coming technologies, which are much smaller, can have a higher defect rate after production, but also at runtime. The physical effects at runtime come from a higher susceptibility for radiation. Since the silicon die of a field programmable gate array (FPGA) includes a high amount of physical wiring, the radiation effect plays here a major role. Therefore, this article describes an approach of a reliable Network-on-Chip (NoC) which can be used for an FPGA-based system. The article describes the concept and the physical realization of this NoC and evaluates its reliability.
- Ali, M., Welzl, M., Hessler, S., and Hellebrand, S. 2007. A Fault tolerant mechanism for handling Permanent and Transient Failures in a Network on Chip. In Proceedings of the 3rd International Conference on Information Technology: New Generations. IEEE Computer Society, Los Alamitos, CA, 1027--1032. Google Scholar
Digital Library
- Baloch, S., Arslan, T., and Stoica, A. 2006. Design of a novel soft error mitigation technique for reconfigurable architectures. In Proceedings of the IEEE Aerospace Conference, 1--9. Google Scholar
Cross Ref
- Coppola, M., Locatelli, R., Maruccia, G., Pieralisi, L., and Scandurra, A. 2004. Spidergon: A novel on-chip communication network. In Proceedings of the International Symposium on System on Chip. IEEE Computer Society, Los Alamitos, CA, 15. Google Scholar
Cross Ref
- Dumitras, T., Kerner, S., and Marculescu, R. 2003. Towards on-chip fault-tolerant communication. In Proceedings of the Asia and South Pacific Design Automation Conference. ACM, New York, NY, 225--232. Google Scholar
Digital Library
- Goehringer, D., Oey, O., Huebner, M., and Becker, J. 2011. Heterogeneous and runtime parameterizable star-wheels network-on-chip. In Proceedings of the 11th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XI). Google Scholar
Cross Ref
- Killian, C., Tanougast, C., Dandache, A., Frihi, M., and Toumi, S. 2011. A dependable and dynamic network on chip suitable for FPGA-based reconfigurable systems. In Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC). 1--6.Google Scholar
- Kim, Y. B. and Kim, Y. B. 2007. Fault tolerant source routing for network-on-chip. In Proceedings of the conference on Defect and Fault-Tolerance in VLSI Systems. IEEE Computer Society, Los Alamitos, CA, 12--20. Google Scholar
Digital Library
- Mavis, D. G. and Eaton, P. H. 2007. SEU and SET Modeling and Mitigation in deep-submicron technologies. In Proceedings of the 45th Annual International Reliability Physics Symposium. 293--305. Google Scholar
Digital Library
- Morgan, K. S., Mcmurtrey, D. L. et. al. 2007. A comparison of TMR with alternative fault-tolerant design techniques for FPGAs, IEEE Trans. Nuclear Science 54, 6, 2065--2072. Google Scholar
Cross Ref
- Paulsson, K., Huebner, M., Jung, M., and Becker, J. 2006. Methods for run-time failure recognition and recovery in dynamic and partial reconfigurable systems based on Xilinx Virtex-II Pro FPGAs. In Proceedings of the IEEE Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06). Google Scholar
Digital Library
- Piretti, M., Link, G. M., Brooks, R. R., Vijaykrishnan, N., Kandemir, M., and Irwin, M. J. 2004. Fault tolerant algorithms for network-on-chip interconnect. In Proceedings of the IEEE Annual Symposium on VLSI. IEEE Computer Society, Los Alamitos, CA, 46--51. Google Scholar
Cross Ref
- Riemzenman, M. J. 1996. Electromigration: the time bomb in the deep-submicron ICs. IEEE Spectrum, 75--78. Google Scholar
Digital Library
- Sedghi, M., Alagi, A., Koopahi, E., and Navabi, Z. 2007. An HDL-Based Platform for High Level NoC Switch Testing. In Proceedings of the 16th Asian Test Symposium. IEEE Computer Society, Los Alamitos, CA, 453--458. Google Scholar
Digital Library
- Xilinx, 2001. Triple Module Redundancy Design - Techniques for Virtex FPGAs. XAPP197 (v1.0) http://www.xilinx.com.Google Scholar
- Xilinx, 2010. Partial Reconfiguration User Guide. UG702 (v12.1). http://www.xilinx.com.Google Scholar
Index Terms
Reliable and adaptive network-on-chip architectures for cyber physical systems
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