Sidharta Andalam
ABSTRACT
Safety-critical systems require guarantees on their worst-case execution times. This requires modelling of speculative hardware features such as caches that are tailored to improve the average-case performance, while ignoring the worst case, which complicates the Worst Case Execution Time (WCET) analysis problem. Existing approaches that precisely compute WCET suffer from state-space explosion. In this paper, we present a novel cache analysis technique for direct-mapped instruction caches with the same precision as the most precise techniques, while improving analysis time by up to 240 times. This improvement is achieved by analysing individual control points separately, and carrying out optimisations that are not possible with existing techniques.
- MicroBlaze Processor Reference Guide. www.xilinx.com (Last accessed: 01/10/2012).Google Scholar
- D. Bui, E. Lee, I. Liu, H. Patel, and J. Reineke. Temporal isolation on multiprocessing architectures. In Proc. of DAC'11, pages 274--279, San Diego, California, June 2011. Google ScholarDigital Library
- H. Ding, Y. Liang, and T. Mitra. WCET-centric partial instruction cache locking. In Proc. of DAC'12, pages 412--420, San Francisco, California, June 2012. Google ScholarDigital Library
- C. Ferdinand, F. Martin, R. Wilhelm, and M. Alt. Cache Behavior Prediction by Abstract Interpretation. Science of Computer Programming, 35:163--189, November 1999. Google ScholarDigital Library
- M. Kuo, R. Sinha, and P. S. Roop. Efficient WCRT Analysis of Synchronous Programs using Reachability. In Proc. of DAC'11, San Diego, USA, June 2011. Google ScholarDigital Library
- M. Kuo, L. H. Yoong, S. Andalam, and P. Roop. Determining the worst-case reaction time of IEC 61499 function blocks. In Proc. INDIN'10, pages 1104--1109, July 2010.Google ScholarCross Ref
- Y.-T. S. Li, S. Malik, and A. Wolfe. Performance estimation of embedded software with instruction cache modeling. ACM Trans. Des. Autom. Electron. Syst., 4(3):257--279, July 1999. Google ScholarDigital Library
- Y. Liang and T. Mitra. Static analysis for fast and accurate design space exploration of caches. In Proc. of CODES+ISSS'08, pages 103--108, Atlanta, GA, USA, 2008. Google ScholarDigital Library
- H. S. Negi, T. Mitra, and A. Roychoudhury. Accurate Estimation of Cache-Related Preemption Delay. In Proc. of CODES+ISSS'03, pages 201--206, CA, USA, 2003. Google ScholarDigital Library
- J. Reineke, D. Grund, C. Berg, and R. Wilhelm. Timing predictability of cache replacement policies. Real-Time Systems, 37(2):99--122, November 2007. Google ScholarDigital Library
- H. Theiling, C. Ferdinand, and R. Wilhelm. Fast and Precise WCET Prediction by Separated Cache and Path Analyses. Real-Time Systems, 18:157--179, 1999. Google ScholarDigital Library
- R. Wilhelm et al. The Worst-Case Execution-Time Problem---Overview of Methods and Survey of Tools. Transactions on Embedded Computing Systems, 7(3):1--53, 2008. Google ScholarDigital Library
Index Terms
- Precise timing analysis for direct-mapped caches
Recommendations
Opportunistic compression for direct-mapped DRAM caches
MEMSYS '18: Proceedings of the International Symposium on Memory SystemsLarge off-chip DRAM caches offer performance and bandwidth improvements for many systems by bridging the gap between on-chip last level caches and off-chip memories. To avoid the high hit latency resulting from serial DRAM accesses for tags and data, ...
WCET Analysis with MRU Caches: Challenging LRU for Predictability
RTAS '12: Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications SymposiumMost previous work in cache analysis for WCET estimation assumes a particular replacement policy called LRU. In contrast, much less work has been done for non-LRU policies, since they are generally considered to be very "unpredictable". However, most ...
Comments