Abstract
Escalating variations in modern CMOS designs have become a threat to Moore’s law. In light of the increasing costs of standard worst-case design practices, timing speculation has become a popular approach for dealing with static and dynamic non-determinism and increasing yield. Timing speculative architectures allow conservative guardbands to be relaxed, increasing efficiency at the expense of occasional errors, which are corrected or tolerated by an error resilience mechanism. Previous work has proposed circuit- or design-level optimizations that manipulate the error rate behavior of a design to increase the efficiency of timing speculation. In this article, we investigate whether architectural optimizations can also manipulate error rate behavior to significantly increase the effectiveness of timing speculation. To this end, we demonstrate how error rate behavior indeed depends on processor architecture and that architectural optimizations can be used to manipulate the error rate behavior of a processor. Using timing speculation-aware architectural optimizations, we demonstrate enhanced overscaling and up to 29% additional energy savings for processors that employ Razor-based timing speculation.
- Bowman, K., Tschanz, J., Wilkerson, C., Lu, S., Karnik, T., De, V., and Borkar, S. 2009. Circuit techniques for dynamic variation tolerance. In Proceedings of DAC. 4--7. Google Scholar
Digital Library
- Brooks, D., Tiwari, V., and Martonosi, M. 2000. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of ISCA. Google Scholar
Digital Library
- Choudhary, N., Wadhavkar, S., Shah, T., Mayukh, H., Gandhi, J., Dwiel, B., Navada, S., Najaf-abadi, H., and Rotenberg, E. 2011. Fabscalar: Composing synthesizable rtl designs of arbitrary cores within a canonical superscalar template. In Proceedings of ISCA. 11--22. Google Scholar
Digital Library
- Dhar, S., Maksimovic, D., and Kranzen, B. 2002. Closed-loop adaptive voltage scaling controller for standard-cell asics. In Proceedings of ISLPED. Google Scholar
Digital Library
- Ernst, D., Kim, N. S., Das, S., Pant, S., Rao, R., Pham, T., Ziesler, C., Blaauw, D., Austin, T., Flautner, K., and Mudge, T. 2003. Razor: A low-power pipeline based on circuit-level timing speculation. In Proceedings of MICRO. 7. Google Scholar
Digital Library
- Fujimura, Y., Hirabayashi, O., Sasaki, T., Suzuki, A., Kawasumi, A., Takeyama, Y., Kushida, K., Fukano, G., Katayama, A., Niki, Y., and Yabe, T. 2010. A configurable sram with constant-negative-level write buffer for low voltage operation with 0.149μm2 cell in 32nm high-k/metal gate cmos. In Proceedings of ISSCC.Google Scholar
- Greskamp, B. and Torrellas, J. 2007. Paceline: Improving single-thread performance in nanoscale cmps through core overclocking. In Proceedings of PACT, 213--224. Google Scholar
Digital Library
- Greskamp, B., Wan, L., Karpuzcu, W., Cook, J., Torrellas, J., Chen, D., and Zilles, C. 2009. Blueshift: Designing processors for timing speculation from the ground up. In Proceedings of HPCA.Google Scholar
- Hamerly, G., Perelman, E., Lau, J., and Calder, B. 2005. Simpoint 3.0: Faster and more flexible program analysis. In Proceedings of JILP.Google Scholar
- Hartstein, A. and Puzak, T. 2003. Optimum power/performance pipeline depth. In Proceedings of MICRO. 117. Google Scholar
Digital Library
- Intel Corporation 2008. Intel Atom Processor Z5xx Series. Intel Corporation. http://www.intel.com/.Google Scholar
- Kahng, A., Kang, S., Kumar, R., and Sartori, J. 2010a. Designing processors from the ground up to allow voltage/reliability tradeoffs. In Proceedings of HPCA.Google Scholar
- Kahng, A., Kang, S., Kumar, R., and Sartori, J. 2010b. Recovery-driven design: A methodology for power minimization for error tolerant processor modules. In Proceedings of DAC. Google Scholar
Digital Library
- Kahng, A., Kang, S., Kumar, R., and Sartori, J. 2010c. Slack redistribution for graceful degradation under voltage overscaling. In Proceedings of ASPDAC. Google Scholar
Digital Library
- Kehl, T. 1993. Hardware self-tuning and circuit performance monitoring. In Proceedings of ICCD, 188--192.Google Scholar
Cross Ref
- Liang, X. and Brooks, D. 2006. Microarchitecture parameter selection to optimize system performance under process variation. In Proceedings of ICCAD. 429--436. Google Scholar
Digital Library
- Narayanan, S., Sartori, J., Kumar, R., and Jones, D. 2010. Scalable stochastic processors. In Proceedings of DATE. Google Scholar
Digital Library
- Palacharla, S., Jouppi, N., and Smith, J. 1997. Complexity-effective superscalar processors. In Proceedings of ISCA. Google Scholar
Digital Library
- Pan, Y., Kong, J., Ozdemir, S., Memik, G., and Chung, S. W. 2009. Selective wordline voltage boosting for caches to manage yield under process variations. In Proceedings of DAC. 57--62. Google Scholar
Digital Library
- Sarangi, S., Greskamp, B., Tiwari, A., and Torrellas, J. 2008. Eval: Utilizing processors with variation-induced timing errors. In Proceedings of MICRO, 423--434. Google Scholar
Digital Library
- Sartori, J. and Kumar, R. 2010. Overscaling-friendly timing speculation architectures. In Proceedings of GLSVLSI. Google Scholar
Digital Library
- Tullsen, D. M. 1996. Simulation and modeling of a simultaneous multithreading processor. In Proceedings of the 22nd Annual Computer Measurement Group Conference.Google Scholar
Index Terms
Exploiting Timing Error Resilience in Processor Architecture
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