skip to main content
research-article

Designing best effort networks-on-chip to meet hard latency constraints

Published:03 July 2013Publication History
Skip Abstract Section

Abstract

Many classes of applications require Quality of Service (QoS) guarantees from the system interconnect. In Networks-on-Chip (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware support in the NoC fabric and its interfaces. In this article we present a novel NoC synthesis framework to automatically build networks that meet hard latency constraints of end-to-end traffic streams without requiring specialized hardware for the network components. The hard latency constraints are met by carefully designing the NoC topology and selecting the appropriate routes for flow using lean best-effort network components. We perform experiments on several System on Chip (SoC) benchmarks. We compared against a topology synthesis method with no support for real-time constraints and we show that the proposed method can produce topologies that can meet significantly tighter worst case latency constraints (on average 44%). We also show that the tightest worst case latency can be provided with little overhead on power consumption (on average 8.5%).

References

  1. Ahonen, T., Sigüenza-Tortosa, D. A., Bin, H., and Nurmi, J. 2004. Topology optimization for application-specific networks-on-chip. In Proceedings of the International Workshop on System Level Interconnect Prediction (SLIP'04). ACM, New York, 53--60. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Bjerregaard, T. and Sparso, J. 2005. A router architecture for connection-oriented service guarantees in the mango clockless network-on-chip. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'05). Vol. 2. IEEE, 1226--1231. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Bolotin, E., Cidon, I., Ginosar, R., and Kolodny, A. 2004. Qnoc: Qos architecture and design process for network on chip. J. Syst. Archit. 50, 2--3, 105--128. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Bouhraoua, A. and Elrabaa, E. 2006. A high-throughput network-on-chip architecture for systems-on-chip interconnect. In Proceedings of the International Symposium on System-on-Chip. 1--4.Google ScholarGoogle Scholar
  5. Cristina Silvano, M. L. and Palermo, G. 2011. Low Power Networks-on-Chip, 1st Ed. Springer. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. De Micheli, G. and Benini, L. 2006. Networks on Chips: Technology and Tools (electronic version). Elsevier, Burlington, MA.Google ScholarGoogle Scholar
  7. Feliciian, F. and Furber, S. 2004. An asynchronous on-chip network router with quality-of-service (QoS) support. In Proceedings of the IEEE International System-on-Chip Conference. 274--277.Google ScholarGoogle Scholar
  8. Flich, J. and Bertozzi, D. 2010. Designing Network On-Chip Architectures in the Nanoscale Era. Chapman & Hall/CRC. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Goossens, K., Dielissen, J., and Radulescu, A. 2005. Aethereal network on chip: concepts, architectures, and implementations. IEEE Des. Test Comput. 22, 5, 414--421. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Hansson, A., Goossens, K., and Radulescu, A. 2005. A unified approach to constrained mapping and routing on network-on-chip architectures. In Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05). ACM, New York, 75--80. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Hendrickson, B. and Leland, R. 1994. The Chaco user's guide: Version 2.0. Sandia Tech rep. SAND942692.Google ScholarGoogle Scholar
  12. Ho, W. and Pinkston, T. 2006. A design methodology for efficient application-specific on-chip interconnects. IEEE Trans Parallel Distrib. Syst. 17, 2, 174--190. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Hu, J. and Marculescu, R. 2003. Exploiting the routing flexibility for energy/performance aware mapping of regular noc architectures. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'03). Vol. 1, IEEE, 10688. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Kavaldjiev, N., Smit, G., and Jansen, P. 2004. A virtual channel router for on-chip networks. In Proceedings of the IEEE International System-on-Chip Conference. 289--293.Google ScholarGoogle Scholar
  15. Kopetz, H., Damm, A., Koza, C., Mulazzani, M., Schwabl, W., Senft, C., and Zainlinger, R. 1989. Distributed fault-tolerant real-time systems: The Mars approach. IEEE Micro 9, 1, 25--40. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Lee, S. 2003. Real-time wormhole channels.J. Parallel Distrib/Comput. 63, 3, 299--311. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Leroy, A., Marchal, P., Shickova, A., Catthoor, F., Robert, F., and Verkest, D. 2005. Spatial division multiplexing: a novel approach for guaranteed throughput on nocs. In Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05). ACM, New York, NY, USA, 81--86. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Marescaux, T. and Corporaal, H. 2007. Introducing the supergt network-on-chip: Supergt qos: more than just gt. In Proceedings of the 44th Annual Design Automation Conference (DAC'07). ACM, New York, 116--121. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Mello, A., Tedesco, L., Calazans, N., and Moraes, F. 2006. Evaluation of current qos mechanisms in networks on chip. In Proceedings of the IEEE International System-on-Chip Conference. 1--4.Google ScholarGoogle Scholar
  20. Millberg, M., Nilsson, E., Thid, R., and Jantsch, A. 2004. Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'04), Vol. 2. IEEE, 20890--. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Mondinelli, F., Borgatti, M., and Vajna, Z. 2004. A 0.13 mu;m 1gb/s/channel store-and-forward network on-chip. In Proceedings of the IEEE International System-on-Chip Conference. 141--142.Google ScholarGoogle Scholar
  22. Mullins, R., West, A., and Moore, S. 2006. The design and implementation of a low-latency on-chip network. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'06). IEEE, 164--169. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Murali, S. and Micheli, G. D. 2004a. Bandwidth-constrained mapping of cores onto noc architectures. In Proceedings of the Conference on Design, Automation and Test in Europe. 20896. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. Murali, S. and Micheli, G. D. 2004b. Sunmap: A tool for automatic topology selection and generation for NoCs. In Proceedings of the Design Automation Conference. 914--919. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. Murali, S., Benini, L., and De Micheli, G. 2005. Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees. Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'05). ACM, New York, 27--32. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. Murali, S., Meloni, P., Angiolini, F., Atienza, D., Carta, S., Benini, L., De Micheli, G., and Raffo, L. 2006. Designing application-specific networks on chips with floorplan information. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'06). ACM, New York, 355--362. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. Paukovits, C. and Kopetz, H. 2008. Concepts of switching in the time-triggered network-on-chip. In Proceedings of the International Workshop on Real-Time Computing Systems and Applications. 120--129. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. Philips. 2004. Philips nexperia highly integrated programmable system-on-chip (mpsoc). http://www. semiconductors.philips.com/products/nexperia.Google ScholarGoogle Scholar
  29. Pinto, A., Carloni, L. P., and Sangiovanni-Vincentelli, A. L. 2003. Efficient synthesis of networks on chip. In Proceedings of the International Conference on Computer Design. 146. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. Radulescu, A., Dielissen, J., Pestana, S., Gangwal, O., Rijpkema, E., Wielage, P., and Goossens, K. 2005. An efficient on-chip ni offering guaranteed services, shared-memory abstraction, and flexible network configuration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24, 1, 4--17. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. Rahmati, D., Murali, S., Benini, L., Angiolini, F., De Micheli, G., and Sarbazi-Azad, H. 2009. A method for calculating hard qos guarantees for networks-on-chip. In Proceedings of the 2009 International Conference on Computer-Aided Design (ICCAD'09). ACM, New York, 579--586. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. Rijpkema, E., Goossens, K., Radulescu, A., Dielissen, J., Van Meerbergen, J., Wielage, P., and Waterlander, E. 2003. Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip. IEE Proc.: Comput. Digital Techn. 150, 5, 294--302.Google ScholarGoogle ScholarCross RefCross Ref
  33. Salminen, E., Kulmala, A., and Hämäläinen, T. 2008. Survey of network-on-chip proposals. http://www. ocpip.org.Google ScholarGoogle Scholar
  34. Seiculescu, C., Murali, S., Benini, L., and De Micheli, G. 2010. Sunfloor 3d: A tool for networks on chip topology synthesis for 3-d systems on chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29, 12, 1987--2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. Shi, Z. and Burns, A. 2008. Real-time communication analysis for on-chip networks with wormhole switching. In Proceedings of the 2nd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'08). IEEE, 161--170. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. Srinivasan, K., Chatha, K. S., and Konjevod, G. 2005. An automated technique for topology and route generation of application specific on-chip interconnection networks. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'05). IEEE, 231--237. Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. Stergiou, S., Angiolini, F., Carta, S., Raffo, L., Bertozzi, D., and Micheli, G. D. 2005. ×pipes lite: A synthesis oriented design library for networks on chips. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'05), Vol. 2. IEEE, 1188--1193. Google ScholarGoogle ScholarDigital LibraryDigital Library
  38. STMIcroelectronics. 2004. ST nomadik multimedia processor. http://www.st.com/stonline/prodpres/dedicate/proc/proc.htm.Google ScholarGoogle Scholar
  39. TI Instruments. 2004. TI's omap platform. http://focus.ti.com/omap/docs/.Google ScholarGoogle Scholar
  40. Xu, J., Wolf, W., Henkel, J., and Chakradhar, S. 2006. A design methodology for application-specific networks-on-chip. ACM Trans. Embed. Comput. Syst. 5, 263--280. Google ScholarGoogle ScholarDigital LibraryDigital Library
  41. Zhu, X. and Malik, S. 2002. A hierarchical modeling framework for on-chip communication architectures. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'02). ACM, New York, 663--671. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Designing best effort networks-on-chip to meet hard latency constraints

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in

    Full Access

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader
    About Cookies On This Site

    We use cookies to ensure that we give you the best experience on our website.

    Learn more

    Got it!