Abstract
Networks-on-chip (NoCs) are key components in many-core chip designs. Dynamic power-awareness is a new challenge present in NoCs that must be efficiently handled by the routing functionality as it introduces irregularities in the commonly used 2-D meshes. In this article, we propose a logic-based routing algorithm, iFDOR, oriented towards dynamic powering down one region within every application partition on the chip through dynamic rerouting, with low implementation costs. Results show that we can successfully shutdown an arbitrary rectangular region within an application partition without significant impact on network performance.
Supplemental Material
Available for Download
Supplemental movie, appendix, image and software files for, Enabling power efficiency through dynamic rerouting on-chip
- Agarwal, N., Peh, L., and Jha, N. 2009. In-network snoop ordering (INSO): Snoopy coherence on unordered interconnects. In Proceedings of the IEEE 15th International Symposium on High Performance Computer Architecture. IEEE, 67--78.Google Scholar
- Alaghi, A., Sedghi, M., Karimi, N., Fathy, M., and Navabi, Z. 2008. Reliable NoC Architecture utilizing a robust rerouting algorithm. In Proceedings of the East-West Design and Test Conference.Google Scholar
- Azimi, M. 2007. Integration challenges and tradeoffs for terascale architectures. Intel Tech. J. 11, 03.Google Scholar
Cross Ref
- Bertozzi, D. 2004. A network-on-chip architecture for gigascale systems-on-chip. IEEE Circuits Syst. Mag.Google Scholar
Cross Ref
- Bogdan, P., Dumitra, T., and Marculescu, R. 2007. Stochastic communication: A new paradigm for fault-tolerant networks-on-chip. VLSI Design 2007, 1--18.Google Scholar
Cross Ref
- Boppana, R. V. and Chalasani, S. 1994. Fault-tolerant routing with non-adaptive wormhole algorithms in mesh networks. In Proceedings of the ACM/IEEE Conference on Supercomputing. 693. Google Scholar
Digital Library
- Boppana, R. V. and Chalasani, S. 1995. Fault-tolerant wormhole routing algorithms for mesh networks. IEEE Trans. Comput. 44, 848--864. Google Scholar
Digital Library
- Camacho, J., Flich, J., Duato, J., Eberle, H., and Olesinski, W. 2011. A Power-Efficient Network On-Chip Topology. ACM Press, New York.Google Scholar
- Casado, R., Bermudez, A., Duato, J., Quiles, F., and Sanchez, J. 2001. A protocol for deadlock-free dynamic reconfiguration in high-speed local area networks. IEEE Trans. Parallel Distrib. Syst. 12, 2, 115--132. Google Scholar
Digital Library
- Chalasani, S. and Boppana, R. V. 1997. Communication in multicomputers with nonconvex faults. IEEE Trans. Comput. 46, 616--622. Google Scholar
Digital Library
- Chen, X. and Peh, L.-S. 2003. Leakage power modeling and optimization in interconnection networks. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'03). 90--95. Google Scholar
Digital Library
- Chiu, G. 2000. The odd-even turn model for adaptive routing. IEEE Trans. Parallel Distrib. Syst. 11, 7, 729--738. Google Scholar
Digital Library
- Duato, J. 1994. A theory of fault-tolerant routing in wormhole networks. In Proceedings of the International Conference on Parallel and Distributed Systems. IEEE, 600--607. Google Scholar
Digital Library
- Fick, D., Deorio, A., Chen, G., Bertacco, V., Sylvester, D., and Blaauw, D. 2009. A highly resilient routing algorithm for fault-tolerant NoCs. In Proceedings of the Conference & Exhibition on Design, Automation and Test in Europe (DATE'09). IEEE, 21--26. Google Scholar
Digital Library
- Ghiribaldi, A., Ludovici, D., Favalli, M., and Bertozzi, D. 2011. System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic. In Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.Google Scholar
- Gilabert, F., Gómez, M. E., Medardoni, S., and Bertozzi, D. 2010. Improved utilization of NoC channel bandwidth by switch replication for cost-effective multi-processor systems-on-chip. In Proceedings of the 4th ACM/IEEE International Symposium on Networks-on-Chip. 165--172. Google Scholar
Digital Library
- Glass, C. and Ni, L. 1994. The turn model for adaptive routing. J. ACM 41, 5, 874--902. Google Scholar
Digital Library
- Gómez, M. E., Flich, J., Nordbotten, N. A., López, P., Robles, A., Duato, J., Skeie, T., and Lysne, O. 2006. A routing methodology for achieving fault tolerance in direct networks. IEEE Trans. Comput. 55, 400--415. Google Scholar
Digital Library
- Hale, K. C., Grot, B., and Keckler, S. W. 2009. Segment gating for static energy reduction in networks-on-chip. In Proceedings of the 2nd International Workshop on Networks on Chip Architectures (NoCArc'09). 57. Google Scholar
Digital Library
- Honarmand, N., Shahabi, A., and Navabi, Z. 2007. A heuristic search algorithm for re-routing of on-chip networks in the presence of faulty links and switches. In Proceedings of the IEEE East-West Design & Test Symposium. 411--416.Google Scholar
- Intel. 2010. Real World technologies - Intel's Sandy Bridge microarchitecture.Google Scholar
- Jha, N. 2003. Dynamic voltage scaling with links for power optimization of interconnection networks. In Proceedings of the 9th International Symposium on High-Performance Computer Architecture. 91--102. Google Scholar
Digital Library
- Kim, H., Ghoshal, P., Grot, B., Gratz, P., and Jiménez, D. 2011. Reducing network-on-chip energy consumption through spatial locality speculation. In Proceedings of the International Workshop on Networks on Chip Architectures Google Scholar
Digital Library
- Kim, S. 1997. Fault-tolerant wormhole routing in mesh with overlapped solid fault regions. Parallel Comput. 23, 13, 1937--1962. Google Scholar
Digital Library
- Lee, J.-G., Shin, W., Kim, S.-J., and Jung, E.-G. 2010. A performance/energy analysis and optimization of multi-core architectures with voltage scaling techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. E93-A, 6, 1215--1225.Google Scholar
Cross Ref
- Lee, S. E. and Bagherzadeh, N. 2009. A variable frequency link for a power-aware network-on-chip (NoC). Integration VLSI J. 42, 4, 479--485. Google Scholar
Digital Library
- Li, F., Chen, G., Kandemir, M., and Kolcu, I. 2007. Profile-driven energy reduction in network-on-chips. ACM SIGPLAN Notices 42, 6, 394. Google Scholar
Digital Library
- Link, G. M. and Vijaykrishnan, N. 2005. Hotspot prevention through runtime reconfiguration in network-on-chip. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'05). IEEE, 648--649. Google Scholar
Digital Library
- Lotfi-Kamran, P., Rahmani, A.M., Daneshtalab, M., Afzali-Kusha, A., and Navabi, Z. 2010. EDXY A low cost congestion-aware routing algorithm for network-on-chips. J. Syst. Archit. 56, 7, 256--264. Google Scholar
Digital Library
- Martin, M., Sorin, D., Ailamaki, A., Alameldeen, A., Dickson, R., Mauer, C., Moore, K., Plakal, M., Hill, M., and Wood, D. 2000. Timestamp snooping: an approach for extending SMPs. ACM SIGPLAN Notices 35, 11, 25--36. Google Scholar
Digital Library
- Martin, M. M. K., Hill, M. D., and Wood, D. A. 2003. Token coherence: Decoupling performance and correctness. ACM SIGARCH Comput. Archite. News 31, 2, 182. Google Scholar
Digital Library
- Matsutani, H., Koibuchi, M., Amano, H., and Wang, D. 2008. Run-time power gating of on-chip routers using look-ahead routing. In Proceedings of the Asia and South Pacific Design Automation Conference. 55--60. Google Scholar
Digital Library
- Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H., and Amano, H. 2010. Ultra fine-grained run-time power gating of on-chip routers for CMPs. In Proceedings of the 4th ACM/IEEE International Symposium on Networks-on-Chip. 61--68. Google Scholar
Digital Library
- Mello, A., Tedesco, L., Calazans, N., and Moraes, F. 2005. Virtual channels in networks on chip: Implementation and evaluation on Hermes NoC. In Proceedings of the 18th Symposium on Integrated Circuits and Systems Design. 178--183. Google Scholar
Digital Library
- Nikitovic, M. and Brorsson, M. 2007. Adaptive shutdown scheduling strategies in chip-multiprocessor platforms for future mobile terminals. CiteSeerX 10.1.1.9.1634.Google Scholar
- Nilsson, E., Millberg, M., Öberg, J., and Jantsch, A. 2003. Load distribution with the proximity congestion awareness in a network-on-chip. In Proceedings of the Conference on Design, Automation and Test in Europe. Google Scholar
Digital Library
- Pinkston, T. M., Pang, R., and Duato, J. 2003. Deadlock-free dynamic reconfiguration schemes for increased network dependability. IEEE Trans. Parallel Distrib. Syst. 14, 780--794. Google Scholar
Digital Library
- Pirretti, M., Link, G., Brooks, R., Vijaykrishnan, N., Kandemir, M., and Irwin, M. 2004. Fault tolerant algorithms for network-on-chip interconnect. In Proceedings of the IEEE Annual Symposium on VLSI. 46--51.Google Scholar
- Powell, M., Falsafi, B., Roy, K., and Vijaykumar, T. 2000. Gated-V/sub dd/: A circuit technique to reduce leakage in deep-submicron cache memories. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'00). ACM. 90--95. Google Scholar
Digital Library
- Robles-Gömez, A., Bermüdez, A., and Casado, R. 2008. Deadlock-free dynamic network reconfiguration based on close up*/down* graphs. In Proceedings of the Euro-Par Parallel Processsing. 1--10. Google Scholar
Digital Library
- Rodrigo, S. 2010. PhD thesis. Universidad Politècnica de Valencia.Google Scholar
- Rodrigo, S., Flich, J., Roca, A., Medardoni, S., Bertozzi, D., Camacho, J., Silla, F., and Duato, J. 2010. Addressing manufacturing challenges with cost-efficient fault tolerant routing. In Proceedings of the 4th ACM/IEEE International Symposium on Networks-on-Chip. 25--32. Google Scholar
Digital Library
- Seiculescu, C., Murali, S., Benini, L., and De Micheli, G. 2009. NoC topology synthesis for supporting shutdown of voltage islands in SoCs. In Proceedings of the 46th ACM/IEEE Design Automation Conference (DAC'09). 822--825. Google Scholar
Digital Library
- Sem-Jacobsen, F. O., Rodrigo, S., and Skeie, T. 2011. iFDOR: Dynamic rerouting on-chip. In Proceedings of the 5th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC'11). ACM, New York, 11--14. Google Scholar
Digital Library
- Skeie, T., Sem-Jacobsen, F. O., Flich, J., Rodrigo, S., Bertozzi, D., and Simone, M. 2009. Flexible DOR routing for virtualization of multicore chips. In Proceedings of the International Symposium on System-on-Chip. Google Scholar
Digital Library
- Solheim, A. G., Lysne, O., and Skeie, T. 2009. RecTOR: A new and efficient method for dynamic network reconfiguration. In Proceedings of the International Euro-Par Conference on Parallel Processing. Google Scholar
Digital Library
- Stensgaard, M. 2008. Renoc: A network-on-chip architecture with reconfigurable topology. In Proceedings of the 2nd ACM/IEEE International Symposium on Networks-on-Chip. 55--64. Google Scholar
Digital Library
- Wang, P.-H., Chen, Y.-M., Yang, C.-L., and Cheng, Y.-J. 2009. A predictive shutdown technique for GPU shader processors. IEEE Comput. Archit. Lett. 8, 1, 9--12. Google Scholar
Digital Library
- Wu, J. 2003. A fault-tolerant and deadlock-free routing protocol in 2D meshes based on odd-even turn model. IEEE Trans. Comput. 52, 9, 1154--1169. Google Scholar
Digital Library
Index Terms
Enabling power efficiency through dynamic rerouting on-chip
Recommendations
An efficient, low-cost routing framework for convex mesh partitions to support virtualization
Special Section on Wireless Health Systems, On-Chip and Off-Chip Network ArchitecturesAt the core of an efficient chip multiprocessors (CMP) is support for unicast and multicast routing, low implementation costs, and the ability to isolate concurrent applications with maximum utilization of the CMP. We present an efficient logic-based ...
A high-performance low-power nanophotonic on-chip network
ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and designOn-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfer, limits the power efficiency and performance scalability of many-core chip-...
Cycle-Accurate Network on Chip Simulation with Noxim
The on-chip communication in current Chip-MultiProcessors (CMP) and MultiProcessor-SoC (MPSoC) is mainly based on the Network-on-Chip (NoC) design paradigm. Unfortunately, it is foreseen that conventional NoC architectures cannot sustain the performance,...






Comments