Abstract
Constant multipliers are widely used in signal processing applications to implement the multiplication of signals by a constant coefficient. However, in some applications, this coefficient remains invariable only during an interval of time, and then, its value changes to adapt to new circumstances. In this article, we present a self-reconfigurable constant multiplier suitable for LUT-based FPGAs able to reload the constant in runtime. The pipelined architecture presented is easily scalable to any multiplicand and constant sizes, for unsigned and signed representations. It can be reprogrammed in 16 clock cycles, equivalent to less than 100 ns in current FPGAs. This value is significantly smaller than FPGA partial configuration times. The presented approach is more efficient in terms of area and speed when compared to generic multipliers, achieving up to 91% area reduction and up to 102% speed improvement for the case-study circuits tested. The power consumption of the proposed multipliers are in the range of those of slice-based multipliers provided by the vendor.
- Bosí, B., Bois, G., and Savaria, Y. 1999. Reconfigurable pipelined 2-D convolvers for fast digital signal processing. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 3, 299--308. Google Scholar
Digital Library
- Bouganis, C.-S., Park, S.-B., Constantinides, G. A., and Cheung, P. Y. K. 2009. Synthesis and optimization of 2D filter designs for heterogeneous FPGAs. ACM Trans. Reconfigurable Technol. Syst. 1, 24:1--24:28. Google Scholar
Digital Library
- Caffarena, G., López, J., Leyva, G., Carreras, and Nieto-Taladriz, O. 2009. Architectural synthesis of fixed-point DSP datapaths using FPGAs. Int. J. Reconfigurable Comput. 1--14. Google Scholar
Digital Library
- Chapman, K. 1996. Constant coefficient multipliers for the “xc4000e”. Tech. rep. XAPP 054, Xilinx Corporation, San Jose, CA.Google Scholar
- Chen, J. and Chang, C.-H. 2009. High-level synthesis algorithm for the design of reconfigurable constant multiplier. IEEE Trans. Comput.-Aid. Des. Integ. Circuits Syst. 28, 12, 1844--1856. Google Scholar
Digital Library
- Compton, K., Li, Z., Cooley, J., Knol, S., and Hauck, S. 2002. Configuration relocation and defragmentation for run-time reconfigurable computing. IEEE Trans. VLSI Syst. 10, 3, 209--220. Google Scholar
Digital Library
- Dandalis, A. and Prasanna, V. 2005. Configuration compression for FPGA-based embedded systems. IEEE Trans. VLSI Syst. 13, 12, 1394--1398. Google Scholar
Digital Library
- Demirsoy, S., Kale, I., and Dempster, A. 2007. Reconfigurable multiplier blocks: Structures, algorithm and applications. Circuits, Syst. Signal Process. 26, 6, 793--827.Google Scholar
Digital Library
- Gustafsson, O. 2007. Lower bounds for constant multiplication problems. IEEE Trans. Circuits Syst. II 54, 11, 974--978.Google Scholar
- Gustafsson, O., Dempster, A. G., Johansson, K., Macleod, M. D., and Wanhammar, L. 2006. Simplified design of constant coefficient multipliers. Circuits, Syst. Signal Process. 25, 2, 225--251.Google Scholar
Cross Ref
- Huang, X., Liang, C., and Ma, J. 2008. System architecture and implementation of MIMO sphere decoders on FPGA. IEEE Trans. VLSI Syst. 16, 2, 188--197. Google Scholar
Digital Library
- Kalra, R. and Lysecky, R. 2010. Configuration locking and schedulability estimation for reduced reconfiguration overheads of reconfigurable systems. IEEE Trans. VLSI Syst. 18, 4, 671--674. Google Scholar
Digital Library
- Mahesh, R. and Vinod, A. 2010. New reconfigurable architectures for implementing FIR filters with low complexity. IEEE Trans. Comput.-Aid. Design Integr. Circuits Syst. 29, 2, 275--288. Google Scholar
Digital Library
- Meher, P. 2010. Novel input coding technique for high-precision LUT-based multiplication for DSP applications. In Proceedings of the 18th IEEE/IFIPVLSI System on Chip Conference (VLSI-SoC). 201--206.Google Scholar
Cross Ref
- Nguyen, H. and Chattejee, A. 2000. Number-splitting with shift-and-add decomposition for power and hardware optimization in linear DSP synthesis. IEEE Trans. VLSI Syst. 8, 4, 419--424. Google Scholar
Digital Library
- Oliver, J. and Boemo, E. 2011. Power estimations vs. power measurements in Cyclone III devices. In Proceedings of the Southern Conference on Programmable Logic. 87--90.Google Scholar
- Park, J., Jeong, W., Mahmoodi-Meimand, H., Wang, Y., Choo, H., and Roy, K. 2004. Computation sharing programmable FIR filter for low-power and high-performance applications. IEEE J. Solid-State Circuits 39, 2, 348--357.Google Scholar
Cross Ref
- Shoufan, A., Wink, T., Molter, H., Huss, S., and Kohnert, E. 2010. A novel cryptoprocessor architecture for the McEliece public-key cryptosystem. IEEE Trans. Comput. 59, 11, 1533--1546. Google Scholar
Digital Library
- Turner, R. and Woods, R. 2004. Highly efficient, limited range multipliers for LUT-based FPGA architectures. IEEE Trans. VLSI Syst. 12, 10, 1113--1118. Google Scholar
Digital Library
- Wilton, S., Ang, S., and Luk, W. 2004. The impact of pipelining on energy per operation in field-programmable gate arrays. In Field-Programmable Logic and Application. Lecture Notes in Computer Science, Vol. 3203. Springer-Verlag, Berlin, 719--728.Google Scholar
- Wirthlin, M. 2004. Constant coefficient multiplication using look-up tables. J. VLSI Signal Process. Syst. 36, 1, 7--15. Google Scholar
Digital Library
- Xu, F., Chang, C.-H., and Jong, C.-C. 2008. A new approach to versatile subexpressions sharing in multiple constant multiplications. IEEE Trans. Circuits Syst. 55, 2, 559--571.Google Scholar
Cross Ref
Index Terms
Self-Reconfigurable Constant Multiplier for FPGA
Recommendations
Design and implementation of modified BCD digit multiplier for digit-by-digit decimal multiplier
AbstractDecimal multiplication is the most common operation in arithmetic applications. This paper presents an area-efficient digit-by-digit decimal multiplier using a modified binary-coded decimal digit multiplier. In general, a Binary-Coded Decimal (BCD)...
Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA
In today's world, high-power computing applications such as image processing, digital signal processing, graphics, robotics require enormous computing power. These applications use matrix operations, especially matrix multiplication. Multiplication ...
A compact FPGA-based montgomery multiplier over prime fields
GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSIThis work describes a compact FPGA hardware architecture for computing modular multiplications over GF(p) using the Montgomery method, suitable for public key cryptography for embedded or mobile systems. The multiplier is parameterizable, allowing to ...






Comments