Abstract
Networks-on-Chip (NoC) enable scalability for future manycore architectures, facilitating parallel communication between multiple cores. Applications running in parallel on a NoC-based architecture can affect each other due to overlapping communication. Quality-of-Service (QoS) must be supported by the communication infrastructure to execute communication-, real-time- and safety-critical applications on such an architecture. Different strategies have been proposed to provide QoS for point-to-point connections. These strategies allow each node to set up a limited number of connections to other nodes.
In this work Virtual Networks (VN) are proposed to enable QoS for regions of a NoC-based architecture. Virtual Networks overcome the limitation of point-to-point connections. A VN behaves like an exclusive physical network. Virtual Networks can be defined and configured during runtime. The size of the VN region and the assigned bandwidth can be adjusted depending on the application requirements. Virtual Networks enable the decoupling of local from global communication. Therefore, the communication of the application mapped into the region is assigned to a Virtual Network established in that specific region. This concept targets packet-switched networks with virtual channels and is realized by an intelligent hardware unit that manages the virtual channel reservation process at system runtime. Virtual Networks can be established and administrated independent of each other, enabling distributed communication resource management.
The proposed concept is implemented as a cycle-accurate SystemC simulation model. The simulation results of executing communicating graphs obtained from real application highlight the usefulness of Virtual Networks by showing improved throughput and reduced delay in the respective scenarios. A hardware implementation demonstrates a low impact on area utilization and power consumption.
- Arteris. 2005. A comparison of network-on-chip and busses. http://www.arteris.com/noc_whitepaper.pdf.Google Scholar
- Benini, L. and De Micheli, G. 2002. Networks on chips: A new soc paradigm. Comput. 35, 1, 70--78. Google Scholar
Digital Library
- Bertozzi, D., Jalabert, A., Murali, S., Tamhankar, R., Stergiou, S., Benini, L., and De Micheli, G. 2005. Noc synthesis flow for customized domain specific multiprocessor systems-on-chip. IEEE Trans. Parall. Distrib. Syst. 16, 2, 113--129. Google Scholar
Digital Library
- Bolotin, E., Cidon, I., Ginosar, R., and Kolodny, A. 2004. QNoC: QoS architecture and design process for network on chip. J. Syst. Archit. 50, 2--3, 105--128. Google Scholar
Digital Library
- Borkar, S. 2007. Thousand core chips: A technology perspective. In Proceedings of the 44th Annual Design Automation Conference (DAC'07). 746--749. Google Scholar
Digital Library
- Chou, C.-L., Ogras, U., and Marculescu, R. 2008. Energy- and performance-aware incremental mapping for networks on chip with multiple voltage levels. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 27, 10, 1866--1879. Google Scholar
Digital Library
- Dally, W. 1992. Virtual-channel flow control. IEEE Trans. Parall. Distrib. Syst. 3, 2, 194--205. Google Scholar
Digital Library
- Flich, J., Rodrigo, S., Duato, J., Sodring, T., Solheim, A., Skeie, T., and Lysne, O. 2008. On the potential of noc virtualization for multicore chips. In Proceedings of the International Conference on Complex, Intelligent and Software Intensive Systems (CISIS'08). 801--810. Google Scholar
Digital Library
- Guerrier, P. and Greiner, A. 2000. A generic architecture for on-chip packet-switched interconnections. In Proceedings of the Conference and Exhibition on Design, Automation and Test in Europe (DATE'00). 250--256. Google Scholar
Digital Library
- Heisswolf, J., Konig, R., and Becker, J. 2012. A scalable noc router design providing qos support using weighted round robin scheduling. In Proceedings of the 10th International Symposium on Parallel and Distributed Processing with Applications (ISPA'12). 625--632. Google Scholar
Digital Library
- Kavaldjiev, N., Smit, G., Jansen, P., and Wolkotte, P. 2006. A virtual channel network-on-chip for gt and be traffic. In Proceedings of the IEEE Annual Symposium on Emerging VLSI Technologies and Architectures. 211--216. Google Scholar
Digital Library
- Kobbe, S., Bauer, L., Lohmann, D., Schroder-Preikschat, W., and Henkel, J. 2011. Distrm: Distributed resource management for on-chip many-core systems. In Proceedings of the 7th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. 199--128. Google Scholar
Digital Library
- Koenig, R., Bauer, L., Stripf, T., Shafique, M., Ahmed, W., Becker, J., and Henkel, J. 2010. Kahrisma: A novel hypermorphic reconfigurable-instruction-set multi-grained-array architecture. In Proceedings of the Conference and Exhibition on Design, Automation and Test in Europe (DATE'10). 819--824. Google Scholar
Digital Library
- Landry, A., Nekili, M., and Savaria, Y. 2005. A novel 2 ghz multi-layer amba high-speed bus interconnect matrix for soc platforms. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'05). Vol. 4. IEEE, 3343--3346.Google Scholar
- Mai, K., Paaske, T., Jayasena, N., Ho, R., Dally, W., and Horowitz, M. 2000. Smart memories: A modular reconfigurable architecture. In Proceedings of the 27th International Symposium on. Computer Architecture. 161--171. Google Scholar
Digital Library
- Ni, L. and Mckinley, P. 1993. A survey of wormhole routing techniques in direct networks. Comput. 26, 2, 62--76. Google Scholar
Digital Library
- Nvidia. 2012. NVIDIA kepler gk110 architecture whitepaper. http://www.nvidia.com/content/PDF/kepler/NVIDIA-Kepler-GK110-Architecture-Whitepaper.pdf.Google Scholar
- Rodrigo, S., Flich, J., Duato, J., and Hummel, M. 2008. Efficient unicast and multicast support for cmps. In Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'08). 364--375. Google Scholar
Digital Library
- Sun, G., Zhang, Y., Li, Y., Su, L., Jin, D., and Zeng, L. 2010. Convex-based dor routing for virtualization of noc. In Proceedings of the IFIP International Conference on Network and Parallel Computing. 462--469. Google Scholar
Digital Library
- Teich, J. 2008. Invasive algorithms and architectures. Inf. Technol. 50, 5, 300--310.Google Scholar
Cross Ref
- Tran, A. T. and Baas, B. 2012. Noctweak: A highly parameterizable simulator for early exploration of performance and energy of networks on-chip. Tech. rep., VLSI Computation Lab, ECE Department, University of California, Davis.Google Scholar
- Wang, X., Yang, M., Jiang, Y., and Liu, P. 2011. On an efficient noc multicasting scheme in support of multiple applications running on irregular sub-networks. Microprocess. Microsyst. 35, 119--129. Google Scholar
Digital Library
- Wiklund, D. and Liu, D. 2003. Socbus: Switched network on chip for hard real time embedded systems. In Proceedings of the 17th International Symposium on Parallel and Distributed Processing (IPDPS'03). 78.1. Google Scholar
Digital Library
Index Terms
Virtual networks -- distributed communication resource management
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