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Improving processor efficiency by statically pipelining instructions

Published:20 June 2013Publication History
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Abstract

A new generation of applications requires reduced power consumption without sacrificing performance. Instruction pipelining is commonly used to meet application performance requirements, but some implementation aspects of pipelining are inefficient with respect to energy usage. We propose static pipelining as a new instruction set architecture to enable more efficient instruction flow through the pipeline, which is accomplished by exposing the pipeline structure to the compiler. While this approach simplifies hardware pipeline requirements, significant modifications to the compiler are required. This paper describes the code generation and compiler optimizations we implemented to exploit the features of this architecture. We show that we can achieve performance and code size improvements despite a very low-level instruction representation. We also demonstrate that static pipelining of instructions reduces energy usage by simplifying hardware, avoiding many unnecessary operations, and allowing the compiler to perform optimizations that are not possible on traditional architectures.

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    • Published in

      cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 48, Issue 5
      LCTES '13
      May 2013
      165 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/2499369
      Issue’s Table of Contents
      • cover image ACM Conferences
        LCTES '13: Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
        June 2013
        184 pages
        ISBN:9781450320856
        DOI:10.1145/2491899

      Copyright © 2013 ACM

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      New York, NY, United States

      Publication History

      • Published: 20 June 2013

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